Abstract: A three-dimensional non-volatile memory device includes horizontal word lines separated from each other in a vertical direction, horizontal ferroelectric layers arranged among the horizontal word lines, the horizontal ferroelectric layers including upper horizontal ferroelectric layers and lower horizontal ferroelectric layers, vertical ferroelectric layers contacting side walls of the horizontal ferroelectric layers and extending in the vertical direction, a semiconductor pillar passing through the horizontal word lines in the vertical direction, and a channel region between the horizontal word lines and the semiconductor pillar, wherein the upper horizontal ferroelectric layers and the lower horizontal ferroelectric layers are separated from each other by an air gap in the vertical direction.

Abstract: Disclosed are semiconductor memory devices and electronic systems including the same. The semiconductor memory device may include a vertical channel perpendicular to a top surface of a substrate, word lines disposed on a first side of the vertical channel and vertically stacked on the substrate, back-gate electrodes disposed on a second side of the vertical channel and vertically stacked on the substrate, a ferroelectric layer disposed between the word lines and the first side of the vertical channel, a first intermediate insulating layer disposed between the ferroelectric layer and the first side of the vertical channel, and a second intermediate insulating layer disposed between the back-gate electrodes and the second side of the vertical channel.

Abstract: In a method of manufacturing a semiconductor device, an insulation layer and a first gate electrode layer are alternately and repeatedly formed on a substrate in a first direction perpendicular to an upper surface of the substrate to form a mold layer. The first gate electrode layer includes silicon doped with impurities having a first conductivity type. An opening is formed through the mold layer to expose the upper surface of the substrate. Portions of the first gate electrode layers adjacent to the opening are removed to form gaps, respectively. Horizontal channels are formed in the gaps, respectively. Each of the horizontal channels includes silicon doped with impurities having a second conductivity type. A vertical gate structure extending in the first direction is formed in the opening. A memory channel structure is formed through the mold layer to contact the upper surface of the substrate.

Abstract: A semiconductor device may include a first substrate structure including a substrate, circuit elements on the substrate, and first bonding layers on the circuit elements, and a second substrate structure on the first substrate structure. The second substrate structure may include a plate layer, an intermediate insulating layer below the plate layer and including silicon nitride, gate electrodes below the intermediate insulating layer and stacked to be spaced apart from each other in a vertical direction, a channel structure in a channel hole passing through the intermediate insulating layer and the gate electrodes and including a semiconductor layer, and second bonding layers connected to the first bonding layers. The channel hole may have a first width in a first portion passing through the gate electrodes and a second width, wider than the first width, in a second portion passing through the intermediate insulating layer.

Abstract: A semiconductor memory device includes a back gate electrode, a gate electrode on the back gate electrode, a channel layer between the gate electrode and the back gate electrode, a gate insulating layer between the channel layer and the gate electrode, and a ferroelectric layer between the back gate electrode and the channel layer.

Abstract: A magnetic memory device includes a loop-type magnetic track having a first part and a second part that are arranged in a counterclockwise direction, a first conductive line on a top surface of the first part, and a second conductive line on a bottom surface of the second part. The magnetic track includes a lower magnetic layer, a spacer layer, and an upper magnetic layer that are sequentially stacked. Each of the first and second conductive lines includes heavy metal. Each of the first and second conductive lines is configured to generate spin-orbit torque caused by current that flows therein. The spin-orbit torque causes magnetic domains in the magnetic track to move in a clockwise direction or in the counterclockwise direction.

Abstract: A semiconductor device includes a source structure, gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to an upper surface of the source structure, and a channel structure extending through the gate electrodes in the first direction, and including a dielectric layer, a charge storage layer, a tunneling layer, a channel layer, and a buried semiconductor layer. The dielectric layer is between the gate electrodes and the charge storage layer. The tunneling layer is between charge storage layer and the channel layer. The channel layer is between the tunneling layer and the buried semiconductor layer. An outer surface of a lower portion of the channel layer is in contact with the source structure, and the dielectric layer includes a ferroelectric material, the channel layer includes an oxide semiconductor material, and the buried semiconductor layer includes silicon (Si).

Abstract: The present invention can determine in advance whether the design RULE is violated by checking the design conditions and design requirements required by the client and the project in the plant engineering stage on the 3D CAD model. The present invention can improve the design quality of plant engineering and minimizing the modification of the drawings occurring during construction by checking whether the various data of the vendor drawings received by the EPC company are accurately reflected to the 3D CAD modeling design.

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate including a cell array region, a connection region, and a block selection region between the cell array and connection regions, a stack structure including horizontal layers vertically stacked on the substrate, each of the horizontal layers including electrode portions extending in a first direction on the cell array and block selection regions and a connecting portion disposed on the connection region to connect the electrode portions in a second direction perpendicular to the first direction, and block selection gate electrodes intersecting sidewalls of the electrode portions of the horizontal layers on the block selection region. Each of the electrode portions includes a first semiconductor region having a first conductivity type on the cell array region and includes a channel dopant region having a second conductivity type different from the first conductivity type on the block selection region.

Abstract: The present invention can determine in advance whether the design RULE is violated by checking the design conditions and design requirements required by the client and the project in the plant engineering stage on the 3D CAD model. The present invention can improve the design quality of plant engineering and minimizing the modification of the drawings occurring during construction by checking whether the various data of the vendor drawings received by the EPC company are accurately reflected to the 3D CAD modeling design.

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate including a cell array region, a connection region, and a block selection region between the cell array and connection regions, a stack structure including horizontal layers vertically stacked on the substrate, each of the horizontal layers including electrode portions extending in a first direction on the cell array and block selection regions and a connecting portion disposed on the connection region to connect the electrode portions in a second direction perpendicular to the first direction, and block selection gate electrodes intersecting sidewalls of the electrode portions of the horizontal layers on the block selection region. Each of the electrode portions includes a first semiconductor region having a first conductivity type on the cell array region and includes a channel dopant region having a second conductivity type different from the first conductivity type on the block selection region.