Abstract: A power system for an electrified vehicle comprising a first power source device, a first converter having a first end connected to the first power source device, a second power source device, a motor driving device comprising a motor and an inverter, a switch device configured to selectively connect a second end of the first converter to the second power source device or the motor driving device, and a controller configured to control the switch device such that the second end of the first converter is connected to the second power source device when the first power source device is charged with power of the second power source device and such that the second end of the first converter is connected to the motor driving device when the motor performs regenerative braking.

Abstract: A free motion headform (FMH) impact performance prediction device using artificial intelligence includes a data processing processor configured to generate an image by extracting a pre-processed test target image, generated by pre-processing test target design data, using a pre-trained model and generate a pre-processed test target distance value by pre-processing the test target design data. The FMH input performance prediction device also includes a machine learning processor configured to concatenate the image generated by extraction on the basis of the pre-trained model and the pre-processed test target distance value and to predict impact performance using a neural network in which parameters are updated by learning based on an image obtained by pre-processing existing design data and existing impact amount data corresponding to the existing design data. The FMH input performance prediction device further includes an output processor configured to output a value learned by the machine learning processor.

Abstract: Disclosed is a high voltage output device having a serial-parallel stack structure of capacitors. The high voltage output device includes a substrate includes a capacitor element and a pillar structure provided on an upper surface of the substrate. The substrate includes a first electrode and a second electrode, which have different potentials from each other. The capacitor element is connected to at least one of the first electrode and the second electrode.

Abstract: The present disclosure relates to an apparatus for controlling movement of an ultrasonic wave generating unit, the apparatus characterized by comprising: a transfer unit for moving the ultrasonic wave generating unit; and a control unit for controlling the operation of the ultrasonic wave generating unit and the transfer unit, wherein the control unit controls the ultrasonic wave generating unit such that, when the ultrasonic wave generating unit moves, ultrasonic waves are irradiated at intervals to the skin on a movement path of the ultrasonic wave generating unit.

Abstract: The present invention relates to low-calorie hot sauces, and more particularly, to hot sauces containing hot spices, acid-resistant thickeners and low-calorie or calorie-free saccharides.

Abstract: The present invention relates to low-calorie hot sauces, and more particularly, to hot sauces containing hot spices, acid-resistant thickeners and low-calorie or calorie-free saccharides.

Abstract: A heat radiation sheet includes a low-hardness insulating heat-radiation layer and a high-heat-radiation insulating layer. Each of the low-hardness insulating heat-radiation layer and the high-heat-radiation insulating layer is formed by mixing a thermoplastic elastomer (TPE), a thermally conductive filler, a flame retardant additive, a process oil, and an additive. A method of manufacturing a heat radiation sheet having a double-layered insulating structure, includes: a first step of forming a mixture by mixing a thermoplastic elastomer (TPE), a thermally conductive filler, a flame retardant additive, a process oil, and an additive; a second step of melt-extruding the mixture at a temperature of 120 ? to 300 ? by a melt extrusion apparatus to from a melt extrudate; a third step of cutting the melt extrudate into a pellet form; and a fourth step of sheeting through melt-extruding the pellet into a sheet form by a melt extrusion apparatus.

Abstract: An integrated circuit includes a processor core, a clock control circuit and a debugging circuit. The processor core processes target software. The clock control circuit determines whether an electrical connection exists between the processor core and an external debugger and generates a determination result. The clock control circuit generates an output clock signal based on the determination result. The external debugger performs a debugging operation for the target software. The output clock signal is selectively activated based on the determination result and an input clock signal. The debugging circuit provides information with respect to the debugging operation for the target software to the external debugger based on the output clock signal.

Abstract: In a method of power control for a system-on-chip, output of at least one of a first wakeup request signal and a second wakeup request signal is controlled such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval threshold. The first wakeup request signal and the second wakeup request signal are one of concurrent and consecutive wakeup request signals.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: An integrated circuit includes a processor core, a clock control circuit and a debugging circuit. The processor core processes target software. The clock control circuit determines whether an electrical connection exists between the processor core and an external debugger and generates a determination result. The clock control circuit generates an output clock signal based on the determination result. The external debugger performs a debugging operation for the target software. The output clock signal is selectively activated based on the determination result and an input clock signal. The debugging circuit provides information with respect to the debugging operation for the target software to the external debugger based on the output clock signal.

Abstract: In a method of power control for a system-on-chip, output of at least one of a first wakeup request signal and a second wakeup request signal is controlled such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval threshold. The first wakeup request signal and the second wakeup request signal are one of concurrent and consecutive wakeup request signals.

Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.

Abstract: Data transfer systems are provided. The data transfer systems include a bridge direct memory access (DMA) device. A first memory is electrically coupled to the bridge DMA device and a second memory is electrically coupled to the bridge DMA device. The bridge DMA device is configured to control data transfer operations between the first memory and the second memory. Direct memory access devices and methods of performing data transfer operations are also provided.