Abstract: A power management integrated circuit (PMIC) includes a dynamic voltage scaling (DVS) block configured to generate an output voltage signal, and a DVS monitoring block including a DVS monitoring code generator, and a safety monitoring unit configured to receive a DVS code and detect an error in the DVS code. The DVS block is configured to generate the output voltage signal based on the DVS code obtained by reflecting a DVS trim code in the DVS regulation code, and the DVS trim code is determined by a characteristic of a first digital-to-analog converter (DAC) included in the DVS block. The DVS monitoring code generator is configured to generate the DVS monitoring code obtained by reflecting a DVS monitoring trim code in the DVS regulation code, and the DVS monitoring trim code is determined by a characteristic of a second DAC included in the DVS monitoring block.

Abstract: An electronic device is provided. The electronic device includes a first power management integrated circuit (PMIC) with a first fault controller connected to a first node and a first interface circuit connected to a second node; a second PMIC with a second fault controller connected to the first node and a second interface circuit connected to the second node; and a third PMIC with a third fault controller connected to the first node and a third interface circuit connected to the second node. The first fault controller is configured to, during a power on sequence or a power off sequence, detect a change in a voltage level of the first node. The first interface circuit is configured to communicate with any one or any combination of the second interface circuit and communication and the third interface circuit based on the change in the voltage level of the first node.

Abstract: An electronic device is provided. The electronic device includes a first power management integrated circuit (PMIC) with a first fault controller connected to a first node and a first interface circuit connected to a second node; a second PMIC with a second fault controller connected to the first node and a second interface circuit connected to the second node; and a third PMIC with a third fault controller connected to the first node and a third interface circuit connected to the second node. The first fault controller is configured to, during a power on sequence or a power off sequence, detect a change in a voltage level of the first node. The first interface circuit is configured to communicate with any one or any combination of the second interface circuit and communication and the third interface circuit based on the change in the voltage level of the first node.