Patents by Inventor Skylar SKRZYNIARZ
Skylar SKRZYNIARZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230359571Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.Type: ApplicationFiled: June 30, 2023Publication date: November 9, 2023Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Patent number: 11726925Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.Type: GrantFiled: August 31, 2022Date of Patent: August 15, 2023Assignee: Mythic, Inc.Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Patent number: 11626884Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.Type: GrantFiled: February 18, 2022Date of Patent: April 11, 2023Assignee: Mythic, Inc.Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Patent number: 11615165Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: GrantFiled: March 5, 2021Date of Patent: March 28, 2023Assignee: Mythic, Inc.Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Publication number: 20220414025Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.Type: ApplicationFiled: August 31, 2022Publication date: December 29, 2022Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Patent number: 11467984Abstract: Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.Type: GrantFiled: February 20, 2019Date of Patent: October 11, 2022Assignee: Mythic, Inc.Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Publication number: 20220173747Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.Type: ApplicationFiled: February 18, 2022Publication date: June 2, 2022Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Patent number: 11296717Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.Type: GrantFiled: December 14, 2020Date of Patent: April 5, 2022Assignee: Mythic, Inc.Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Publication number: 20210143832Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.Type: ApplicationFiled: December 14, 2020Publication date: May 13, 2021Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Patent number: 10977339Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: GrantFiled: November 14, 2019Date of Patent: April 13, 2021Assignee: Mythic, Inc.Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Patent number: 10903844Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.Type: GrantFiled: November 14, 2019Date of Patent: January 26, 2021Assignee: Mythic, Inc.Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Publication number: 20200081937Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Publication number: 20200083897Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Patent number: 10523230Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.Type: GrantFiled: July 2, 2019Date of Patent: December 31, 2019Assignee: Mythic, Inc.Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Patent number: 10515136Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: GrantFiled: May 2, 2019Date of Patent: December 24, 2019Assignee: Mythic, Inc.Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Publication number: 20190326921Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick
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Patent number: 10452745Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: GrantFiled: April 24, 2019Date of Patent: October 22, 2019Assignee: Mythic, Inc.Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Patent number: 10409889Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: GrantFiled: December 17, 2018Date of Patent: September 10, 2019Assignee: Mythic, Inc.Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Publication number: 20190258695Abstract: Systems and methods of configuring a fixed memory array of an integrated circuit with coefficients of one or more applications includes identifying a utilization constraint type of the fixed memory array from a plurality of distinct utilization constraint types based on computing attributes of the one or more applications; identifying at least one coefficient mapping technique from a plurality of distinct coefficient mapping techniques that addresses the utilization constraint type; configuring the fixed memory array according to the at least one coefficient mapping technique, wherein configuring the array includes at least setting within the array the coefficients of the one or more applications in an arrangement prescribed by the at least one coefficient mapping technique that optimizes a computational utilization of the fixed memory array.Type: ApplicationFiled: May 2, 2019Publication date: August 22, 2019Inventors: David Fick, Michael Henry, Laura Fick, Malav Parikh, Skylar Skrzyniarz, Scott Johnson, Pei-Ci Wu, Andrew Morten
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Patent number: 10389375Abstract: A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.Type: GrantFiled: February 26, 2019Date of Patent: August 20, 2019Assignee: Mythic, Inc.Inventors: Laura Fick, Manar El-Chammas, Skylar Skrzyniarz, David Fick