Abstract: A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).

Abstract: Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.

Abstract: Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.

Abstract: A master phase locked loop device is operable in association with one or more slave devices including slave digitally controlled oscillators (sDCOs), one or more digital PLL (DPLL) channels include a master digitally controlled oscillator (mDCO). A master synchronization timer generating master timing pulses to read phase and frequency information from the mDCO(s). A peripheral interface sends the read frequency and phase information to the one or more slave devices. A synchronization interface sends the master timing pulses to synchronize a replica synchronization timer in the sDCO(s) that generates slave timing pulses for use in updating the phase and frequency information received at the slave device(s).

Abstract: A universal input buffer has a pair of input pins. A first input of a multiplexer is coupled to the second input pin and a second input of the multiplexer receives a common mode voltage of a differential signal applied to the first pin. The multiplexer is responsive to a selection signal to select either of the first and second inputs of said multiplexer. A pair of single-input buffers have inputs coupled respectively to the first and second input pins. A first input of a first differential buffer is coupled to the first input pin, a first input of a second differential buffer is coupled to the second input pin, the second input of the first differential buffer is coupled to the output of the multiplexer, and the second input of the second differential buffer receives a common mode voltage of a differential signal applied to the second pin.

Abstract: A universal input buffer has a pair of input pins. A first input of a multiplexer is coupled to the second input pin and a second input of the multiplexer receives a common mode voltage of a differential signal applied to the first pin. The multiplexer is responsive to a selection signal to select either of the first and second inputs of said multiplexer. A pair of single-input buffers have inputs coupled respectively to the first and second input pins. A first input of a first differential buffer is coupled to the first input pin, a first input of a second differential buffer is coupled to the second input pin, the second input of the first differential buffer is coupled to the output of the multiplexer, and the second input of the second differential buffer receives a common mode voltage of a differential signal applied to the second pin.

Abstract: A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks.

Abstract: A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks.

Abstract: A digital phase locked loop has a phase acquisition module that outputs a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference. A phase offset write module convert a phases offset commanded from an external source into a phase offset correction value expressed with respect to the internal phase reference. A phase offset controller sums the phase offset correction values to produce a second phase value, which is added to the first phase value to produce a third phase value expressed with respect to the internal phase reference. A digital controlled oscillator (DCO) outputs a fourth phase value expressed with respect to the internal phase reference. A phase detector outputs a fifth phase value representing the difference between the third and fourth phase values. A loop filter derives a frequency offset for the DCO based on the fifth phase value. An output module generates one or more output clocks from the fourth phase value.

Abstract: A digital phase locked loop has a phase acquisition module that outputs a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference. A phase offset write module convert a phases offset commanded from an external source into a phase offset correction value expressed with respect to the internal phase reference. A phase offset controller sums the phase offset correction values to produce a second phase value, which is added to the first phase value to produce a third phase value expressed with respect to the internal phase reference. A digital controlled oscillator (DCO) outputs a fourth phase value expressed with respect to the internal phase reference. A phase detector outputs a fifth phase value representing the difference between the third and fourth phase values. A loop filter derives a frequency offset for the DCO based on the fifth phase value. An output module generates one or more output clocks from the fourth phase value.

Abstract: A digital FM transmitter has a digital controlled oscillator for generating a modulated RF carrier. A digital signal processor receives digital input samples and generates a modulating signal for input to the digital controlled oscillator. A bandpass filter for filters frequency components of the modulated carrier outside a predetermined frequency band and supplies the filtered modulated RF carrier to an antenna.

Abstract: A digitally controlled oscillator (DCO) generating an output clock includes a jitter shaping module for shifting low frequency digital jitter on the output clock into higher frequency jitter.

Abstract: A digital FM transmitter has a digital controlled oscillator for generating a modulated RF carrier. A digital signal processor receives digital input samples and generates a modulating signal for input to the digital controlled oscillator. A bandpass filter for filters frequency components of the modulated carrier outside a predetermined frequency band and supplies the filtered modulated RF carrier to an antenna.

Abstract: A digitally controlled oscillator (DCO) generating an output clock includes a jitter shaping module for shifting low frequency digital jitter on the output clock into higher frequency jitter.