Abstract: The current application is directed to maintaining the correct number of symbols in a protocol frame in a digital communications receiver, to prevent catastrophic failure due to dynamic multipath or cycle slips. Timing recovery and framing are coherent, facilitated by placing channel estimation directly into a larger timing recovery loop.

Abstract: The current document is related to the equalization of digital communications signals, including GB 20600-2006 and ATSC digital television signals, and is directed to methods that initialize adaptive filters for processing payload data within equalizers. These methods may operate at a clock speed faster than the symbol transmission rate and are applicable to a multitude of digital communications standards and protocols. In certain implementations, the initialization method generates input records, from output of a pseudorandom number generator, and output records, from the output of a pseudorandom number generator and a channel estimate, that are decoupled from transmitted and received data and are used to adjust equalizer coefficients to an initialization setting suitable for processing payload data.

Abstract: Certain embodiments of the present invention encapsulate a variety of data, for example, FIC data, together with ATSC-M/H Service data, into a single IP stream, to simplify the interface between demodulator and media processor. A single data interface protocol within the receiver can then be used, facilitating integration.

Abstract: The current application is directed to joint decoding and equalization using a decision feedback equalizer. An example method to which the current application and certain of the current claims are directed uses joint trellis decoding and decision feedback equalization to efficiently estimate non-contiguous symbols using non-contiguous equalizer outputs. The estimation process uses all new possibilities of symbol values, rather than old decision feedback symbol estimates.

Abstract: The current application is directed to maintaining the correct number of symbols in a protocol frame in a digital communications receiver, to prevent catastrophic failure due to dynamic multipath or cycle slips. Timing recovery and framing are coherent, facilitated by placing channel estimation directly into a larger timing recovery loop.

Abstract: The current application is directed to reducing the implementation cost of least squares (LS) channel estimation in a digital communications receiver. An inverse correlation matrix is compressed on a per-diagonal basis for low cost storage in the receiver. The inverse correlation matrix is decompressed and utilized online on a per-diagonal basis.

Abstract: The present invention is related to joint trellis decoding and equalization using a decision feedback equalizer.

Abstract: Certain embodiments of the present invention encapsulate a variety of data, for example, FIC data, together with ATSC-M/H Service data, into a single IP stream, to simplify the interface between demodulator and media processor. A single data interface protocol within the receiver can then be used, facilitating integration.

Abstract: Methods and apparatus for remote antenna subsystems that are physically isolated from receiver subsystems are disclosed. The communication between the two subsystems uses remote communication links. The remote communication links are either wireless, in which case they are designed for indoor low power communications, or are wired, using existing infrastructure in the household such as the power lines. Partitioning between the antenna and receiver subsystems is selectable.

Abstract: The present invention is related to channel identification, equalizer initialization, and framing synchronization of GB 20600-2006 digital television signals. In one embodiment, the present invention provides, in a communications receiver having an equalizer that processes GB 20600-2006 digital television signals that include payload data, a method that initializes the equalizer coefficients for processing the payload data comprising: identifying a channel estimate based on correlation techniques; producing known, mock received data and filtering the mock, received data through the channel estimate to produce mock filtered data; adjusting the equalizer coefficients with the mock received data or the mock filtered data to obtain an initial equalizer setting; and processing the payload data with the initial equalizer setting.

Abstract: The present invention is related to the digital implementation of adaptive equalizers for high-speed communication systems, using finite precision arithmetic, for example, as implemented in a silicon ASIC.

Abstract: The present invention is related to joint trellis decoding and equalization using a decision feedback equalizer.

Abstract: Methods and apparatus for remote antenna subsystems that are physically isolated from receiver subsystems are disclosed. The communication between the two subsystems uses remote communication links. The remote communication links are either wireless, in which case they are designed for indoor low power communications, or are wired, using existing infrastructure in the household such as the power lines. Partitioning between the antenna and receiver subsystems is selectable.

Abstract: Data processing apparatus and methods capable of executing vector instructions. Such apparatus preferably include a number of data buffers whose sizes are configurable in hardware and/or in software; a number of buffer control units adapted to control access to the data buffers, at lease one buffer control unit including at least one programmable write pointer register, read pointer register, read stride register and vector length register; a number of execution units for executing vector instructions using input operands stored in data buffers and storing produced results to data buffers; and at least one Direct Memory Access channel transferring data to and from said buffers. Preferably, at least some of the data buffers are implemented in dual-ported fashion in order to allow at least two simultaneous accesses per buffer, including at least one read access and one write access.

Abstract: A CPU has an execution unit for operating on data under instruction control. A cache and a buffer register are coupled in parallel to an input of the execution unit. The buffer register supplies an information item, such as data or an instruction, to the execution unit upon the cache having completed a refill process.

Abstract: A logic signal validity verifier for use in determining the validity of the logic states of a group of logic signals includes an inactive signal fault monitor for determining when all of the logic signals are in an inactive signal state and an active signal fault monitor for determining when more than one of the logic signals are in an active signal state. Where the logic signals are differential, the logic signal validity verifier further includes a differential signal fault monitor for determining when corresponding pairs of the differential logic signals are in the same active or inactive signal state.