Abstract: A protection device and a method for manufacturing integrated circuit devices protect against plasma charge damage, and related charge damage during manufacture. The protection device comprises a dynamic threshold, NMOS/PMOS pair having their respective gate terminals coupled to the semiconductor bulk in which the channel regions are formed. With proper metal connection, the structure protects against plasma charge damage on the integrated circuit device during manufacture, and can also be operated to protect against abnormal voltages during operation of the circuit.

Abstract: The present invention includes methods to pre-erase non-volatile memory cells using an electrical erase signal prior to dividing a wafer into dies. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: A protection device and a method for manufacturing integrated circuit devices protect against plasma charge damage, and related charge damage during manufacture. The protection device comprises a dynamic threshold, NMOS/PMOS pair having their respective gate terminals coupled to the semiconductor bulk in which the channel regions are formed. With proper metal connection, the structure protects against plasma charge damage on the integrated circuit device during manufacture, and can also be operated to protect against abnormal voltages during operation of the circuit.

Abstract: The present invention includes methods to pre-erase non-volatile memory cells using an electrical erase signal prior to dividing a wafer into dies. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: An flash memory erase method. A bias Vg is applied to a gate of a memory cell. A bias Vd is applied to a source/drain region of the memory cell to execute an erase operation. The bias Vd is increased from an initial value to a predetermined value over time. During the increase of the bias Vd, no inspection is performed. Whether the memory of each memory cell has been erased is inspected. If the erase operation is complete, the erase operation is over. If not, a voltage raise erase-inspection step is performed at least once until it is confirmed that the memory of all the memory cells has been erase. Each voltage raise erase-inspection step includes an erase step with a raised voltage and an inspection step afterwards.

Abstract: An flash memory erase method. A bias Vg is applied to a gate of a memory cell. A bias Vd is applied to a source/drain region of the memory cell to execute an erase operation. The bias Vd is increased from an initial value to a predetermined value over time. During the increase of the bias Vd, no inspection is performed. Whether the memory of each memory cell has been erased is inspected. If the erase operation is complete, the erase operation is over. If not, a voltage raise erase-inspection step is performed at least once until it is confirmed that the memory of all the memory cells has been erase. Each voltage raise erase-inspection step includes an erase step with a raised voltage and an inspection step afterwards.

Abstract: A method of stabilizing a reference bit of a multi-bit memory cell. A first bit of a multi-bit memory cell is pre-programmed to high during fabrication. While reading the multi-bit memory cell, another bit other than the first bit is read as a reference bit.

Abstract: The present invention provides a protection circuit comprising one diode wherein the diode is formed by diffusing a heavily doped material of a first conductivity type into a first region of a second conductivity type. An integrated circuit, such as a memory array, is coupled to the diode. The other diode back-to-back is coupled to the diode wherein the other diode is formed by diffusing a heavily doped material of the second conductivity type into the first region and a second region of the first conductivity type. The two diodes in series are capable of discharging for the memory array during manufacturing process.