Patents by Inventor Smita SHRIDHARAN
Smita SHRIDHARAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11973032Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: GrantFiled: March 8, 2023Date of Patent: April 30, 2024Assignee: Intel CorporationInventors: Smita Shridharan, Zheng Guo, Eric A. Karl, George Shchupak, Tali Kosinovsky
-
Publication number: 20230317612Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BMO) and a backside of an epitaxial structure to provide SRAM VCC voltage (SVCC) voltage, as well as electrical connection structures that electrically couple the BMO to a front side of an epitaxial structure to provide SVCC voltage. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Clifford ONG, Zheng GUO, Eirc A. KARL, Smita SHRIDHARAN, Mauro J. KOBRINSKY, Shem O. OGADHOH, Clifford J. ENGEL, Charles H. WALLACE, Leonard P. GULER
-
Publication number: 20230317148Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Clifford ONG, Leonard P. GULER, Smita SHRIDHARAN, Zheng GUO, Charles H. WALLACE, Eric A. KARL, Mauro J. KOBRINSKY, Shem O. OGADHOH, Tahir GHANI
-
Publication number: 20230320057Abstract: Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Clifford Ong, Leonard Guler, Mohit Haran, Smita Shridharan, Reken Patel, Charles Wallace, Chanaka Munasinghe, Pratik Patel
-
Publication number: 20230223339Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Inventors: Smita SHRIDHARAN, Zheng GUO, Eric A. KARL, George SHCHUPAK, Tali KOSINOVSKY
-
Publication number: 20230209799Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Applicant: Intel CorporationInventors: Clifford Ong, Dan Lavric, Leonard Guler, YenTing Chiu, Smita Shridharan, Zheng Guo, Eric A. Karl, Tahir Ghani
-
Publication number: 20230209797Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Applicant: Intel CorporationInventors: Clifford Ong, Leonard Guler, Smita Shridharan, Zheng Guo, Eric Karl, Tahir Ghani
-
Patent number: 11640939Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: GrantFiled: November 11, 2021Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Smita Shridharan, Zheng Guo, Eric A. Karl, George Shchupak, Tali Kosinovsky
-
Publication number: 20220077055Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: ApplicationFiled: November 11, 2021Publication date: March 10, 2022Inventors: Smita SHRIDHARAN, Zheng GUO, Eric A. KARL, George SHCHUPAK, Tali KOSINOVSKY
-
Patent number: 11205616Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: GrantFiled: June 20, 2017Date of Patent: December 21, 2021Assignee: Intel CorporationInventors: Smita Shridharan, Zheng Guo, Eric A. Karl, George Shchupak, Tali Kosinovsky
-
Publication number: 20200098682Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: ApplicationFiled: June 20, 2017Publication date: March 26, 2020Inventors: Smita SHRIDHARAN, Zheng GUO, Eric A. KARL, George SHCHUPAK, Tali KOSINOVSKY