Patents by Inventor Smitha Banavikal Math Veerabhadresh

Smitha Banavikal Math Veerabhadresh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scalable VLIW processor for high-speed viterbi and trellis coded modulation decoding
    Patent number: 8255780
    Abstract: An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: August 28, 2012
    Assignee: Saankhya Labs Pvt Ltd.
    Inventors: Anindya Saha, Hemant Mallapur, Santhosh Billava, Smitha Banavikal Math Veerabhadresh