Abstract: Embodiments of the invention are directed to a computer-implemented method of performing routing operations for an integrated circuit (IC) design. The computer-implemented method includes identifying, using a processor system, a location of a buffer bay in the IC design. One or more blockage areas associated with the buffer bay are identified. A pattern of the one or more blockage areas is determined, and the pattern includes one or more blockage area exit locations. A component is placed within the buffer bay. Based at least in part on information of the pattern, a routing path is determined from the component through the pattern to one of the one or more blockage area exit locations.

Abstract: Aspects of the invention include optimization of via mesh specifications in an integrated circuit. Aspects include obtaining a first mesh specification for a cell within an integrated circuit, identifying, based on a simulation of a first via mesh built based on the first via mesh specification, portions of the first mesh specification for enhancement, and generating a second mesh specification for the cell, wherein the second mesh specification is different from the first mesh specification. Aspects also include generating a second via mesh based on the second via mesh specification, updating a design of the integrated circuit by replacing the first via mesh with the second via mesh and connecting a top layer of the second via mesh to the net, and saving the updated design of the integrated circuit based on a determination that the updated design of the integrated circuit passes a timing and design rule check.

Abstract: Embodiments of the present disclosure provide methods, systems, and computer program products for implementing retargeting-aware metal fill optimization for an IC layout. A disclosed embodiment enables a metal fill optimization design tool to identify empty space adjacent to the active metal shapes of one or more signal path nets in a metal shapes infrastructure and provide retargeting-aware metal fill insertion into empty space configured to specifically avoid foundry retargeting operations having adverse impacts on timing characteristics of signal path nets.

Abstract: Embodiments herein describe thermal transfer vias and via structures of a semiconductor structure, and methods for implementing thermal transfer vias and via structures for enhanced thermal transfer in the semiconductor structure of integrated circuit designs. A disclosed thermal transfer via comprises a conductive material for thermally transferring heat, and a via structure comprises at least one thermal transfer via providing enhanced thermal transfer in the semiconductor structure of an integrated circuit design.

Abstract: Aspects of the invention include generating a set of via mesh specifications for a cell within an integrated circuit. Each via mesh specification defines one or more straps on each layer above a first layer, which includes one or more pins that form a pin terminal, to a top layer that connects the cell to a net for interconnection of the cell with one or more other cells, and also one or more vias that interconnect adjacent ones of the layers. Aspects also include verifying whether each via mesh specification is a universally routable via mesh specification guaranteeing that the cell interconnects with other cells through the net while meeting all design rules, and including only the via mesh specifications of the set of via mesh specifications that are universally routable in a library of via mesh specifications. The library is used to finalize and fabricate the integrated circuit.

Abstract: Methods for treating tumors comprising cells overexpressing ErbB2 or ErbB3 are provided, and comprise inhibiting the biologic activity of one or more of ErbB2 and ErbB3 in the cells and inhibiting the expression or the biologic activity of a constituent of a signal pathway connected with ErbB2 or ErbB3 signaling.