Abstract: In one embodiment, a processor includes: at least one first core to execute instructions; at least one second core to execute instructions; and a control circuit coupled to the at least one first core and the at least one second core. The control circuit may be configured to: receive workload telemetry information regarding a workload for execution on the processor; determine a QoS distribution based at least in part on the workload telemetry information; receive a predicted workload type, the predicted workload type based at least in part on the QoS distribution; and cause at least one of the at least one first core or the at least one second core to be parked based on the predicted workload type and the QoS distribution. Other embodiments are described and claimed.

Abstract: Embodiments of apparatuses, methods, and systems for resource control based on software priority are described. In embodiments, an apparatus includes resource sharing hardware and multiple cores. The resource sharing hardware is to share the shared resource among the cores. A first core includes first execution circuitry to execute multiple threads. The first core also includes registers programmable by software. A first register is to store a first identifier of a first thread and a first priority tag to indicate a first priority of the first thread relative to a second priority of a second thread. A second register to store a second identifier of the second thread and a second priority tag to indicate the second priority of the second thread relative to the first priority of the first thread. The resource sharing hardware is to use the first priority and the second priority to control access to the shared resource by the first thread and the second thread.

Abstract: In one embodiment, a processor includes one or more cores including a cache memory hierarchy; a performance monitor coupled to the one or more cores, the performance monitor to monitor performance of the one or more cores, the performance monitor to calculate pipeline cost metadata based at least in part on count information associated with the cache memory hierarchy; and a power controller coupled to the performance monitor, the power controller to receive the pipeline cost metadata and determine a low power state for the one or more cores to enter based at least in part on the pipeline cost metadata. Other embodiments are described and claimed.