Patents by Inventor Snehamay Sinha
Snehamay Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230363083Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Inventors: Snehamay Sinha, Tapobrata Bandyopadhyay, Markarand Ramkrishna Kulkarni
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Patent number: 11804382Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.Type: GrantFiled: March 29, 2022Date of Patent: October 31, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaimal Mallory Williamson, Snehamay Sinha
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Patent number: 11800636Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.Type: GrantFiled: September 23, 2021Date of Patent: October 24, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Snehamay Sinha, Tapobrata Bandyopadhyay, Markarand Ramkrishna Kulkarni
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Publication number: 20220319950Abstract: An electronic device includes a multilevel package substrate, a die, a lid, and a package structure that encloses the die, a portion of the lid, and a portion of the multilevel package substrate, where the package structure fills a gap between a side of another portion of the lid and a side of the die. A method includes attaching a die to a multilevel package substrate with a first side of the die facing the multilevel package substrate and a second side facing away from the multilevel package substrate; positioning a lid on the multilevel package substrate with a first portion of the lid spaced apart from the second side of the die; and forming a package structure that encloses the die and a portion of the multilevel package substrate and fills a gap between the first portion of the lid and the second side of the die.Type: ApplicationFiled: October 26, 2021Publication date: October 6, 2022Applicant: Texas Instruments IncorporatedInventors: Hiep Xuan Nguyen, Jaimal Mallory Wiliamson, Arvin Nono Verdeflor, Snehamay Sinha
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Publication number: 20220223509Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Inventors: Jaimal Mallory Williamson, Snehamay Sinha
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Patent number: 11289412Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.Type: GrantFiled: February 20, 2020Date of Patent: March 29, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaimal Mallory Williamson, Snehamay Sinha
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Publication number: 20220015225Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.Type: ApplicationFiled: September 23, 2021Publication date: January 13, 2022Inventors: Snehamay Sinha, Tapobrata Bandyopadhyay, Markarand Ramkrishna Kulkarni
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Patent number: 11160163Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.Type: GrantFiled: November 17, 2017Date of Patent: October 26, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Snehamay Sinha, Tapobrata Bandyopadhyay, Makarand Ramkrishna Kulkarni
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Publication number: 20200294899Abstract: A semiconductor package includes a multilayer substrate including a dielectric layer, a first conductive layer forming a first set of electrical contacts, a second conductive layer forming package electrical contacts and two capacitor electrical contacts, conductive vias extending through the dielectric layer between the first conductive layer with the second conductive layer, and a solder mask layer over the second conductive layer. The semiconductor package further includes a semiconductor die on the first side of the multilayer substrate electrically connected a capacitor on the second side of the multilayer substrate. A recessed portion of the capacitor is within a capacitor opening of the solder mask layer between the two capacitor electrical contacts and a board-side surface of the solder mask layer.Type: ApplicationFiled: February 20, 2020Publication date: September 17, 2020Inventors: Jaimal Mallory Williamson, Snehamay Sinha
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Publication number: 20190159333Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.Type: ApplicationFiled: November 17, 2017Publication date: May 23, 2019Inventors: SNEHAMAY SINHA, TAPOBRATA BANDYOPADHYAY, MAKARAND RAMKRISHNA KULKARNI
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Patent number: 7281223Abstract: The teachings of the present invention provide a method for modeling an integrated circuit system including a microchip, an integrated circuit package, and a printed circuit board. The method includes generating a configuration file including parasitics regarding ball grid arrays and vias intended for use in design of the integrated circuit system. A netlist may be generated using the configuration file. In accordance with a particular embodiment of the present invention, the operation of the integrated circuit system may be simulated to determine anticipated operating characteristics of the integrated circuit system.Type: GrantFiled: December 16, 2004Date of Patent: October 9, 2007Assignee: Texas Instruments IncorporatedInventors: Stephen N. Kiel, Snehamay Sinha, Gregory E. Howard
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Publication number: 20060048081Abstract: The teachings of the present invention provide a method for modeling an integrated circuit system including a microchip, an integrated circuit package, and a printed circuit board. The method includes generating a configuration file including parasitics regarding ball grid arrays and vias intended for use in design of the integrated circuit system. A netlist may be generated using the configuration file. In accordance with a particular embodiment of the present invention, the operation of the integrated circuit system may be simulated to determine anticipated operating characteristics of the integrated circuit system.Type: ApplicationFiled: December 16, 2004Publication date: March 2, 2006Inventors: Stephen Kiel, Snehamay Sinha, Gregory Howard
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Patent number: 6986113Abstract: A method for estimating noise in an integrated circuit substrate. A model file is created for a technology process for fabricating the integrated circuit. Noise generated by a digital circuit and input/output circuitry to be implemented in the integrated circuit are estimated. A substrate netlist is generated for the integrated circuit. A floorplan is determined for the integrated circuit. Transient simulations are run with predetermined input values. Finally, it is determined if predetermined noise requirements are met in results of the transient simulations.Type: GrantFiled: November 10, 2003Date of Patent: January 10, 2006Assignee: Texas Instruments IncorporatedInventors: Snehamay Sinha, Bipasha Ghosh, Raghu Nandan Srinivasa, Stephen N. Kiel
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Publication number: 20040187085Abstract: A method for estimating noise in an integrated circuit substrate. A model file is created for a technology process for fabricating the integrated circuit. Noise generated by a digital circuit and input/output circuitry to be implemented in the integrated circuit are estimated. A substrate netlist is generated for the integrated circuit. A floorplan is determined for the integrated circuit. Transient simulations are run with predetermined input values. Finally, it is determined if predetermined noise requirements are met in results of the transient simulations.Type: ApplicationFiled: November 10, 2003Publication date: September 23, 2004Inventors: Snehamay Sinha, Bipasha Ghosh, Raghu Nandan Srinivasa, Stephen N. Kiel
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Patent number: 6553542Abstract: For simulating electrostatic discharge and latch-up in semiconductor devices, the disclosed system and method for extracting parasitic devices combine input data from device layout, technology rules and doping profiles in order to extract netlists, element location and substrate resistance, analyze the layout for parasitic device formation, store these lists in a verification data base, translate the data base into a specific format, and finally output lists of ESD- and latch-up-sensitive elements and their locations in a specific format such as SPICE format.Type: GrantFiled: February 1, 2001Date of Patent: April 22, 2003Assignee: Texas Instruments IncorporatedInventors: Sridhar Ramaswamy, Snehamay Sinha, Gopalarao Kadamati, Ranjit Gharpurey
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Patent number: 6493850Abstract: For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.Type: GrantFiled: February 16, 2001Date of Patent: December 10, 2002Assignee: Texas Instruments IncorporatedInventors: Puvvada Venugopal, Snehamay Sinha, Sridhar Ramaswamy, Charvaka Duvvury, Guru C. Prasad, C. S. Raghu, Gopalaro Kadamati
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Publication number: 20020152447Abstract: For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabricated), the disclosed computer system and method combine information from the design netlist, the elements model, a safe operating file, and a list of stress simulations, and apply a simulated, quantified ESD event to the design. The observed sensitivities of the design elements to ESD and latch-up are then quantitatively analyzed, critical stress values are judged, and element failures recorded. Finally, element and location lists of sensitivities and failures are output in a specific format.Type: ApplicationFiled: February 16, 2001Publication date: October 17, 2002Inventors: Puvvada Venugopal, Snehamay Sinha, Sridhar Ramaswamy, Charvaka Duvvury, Guru C. Prasad, C.S. Raghu, Gopalaro Kadamati
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Publication number: 20020144213Abstract: For simulating electrostatic discharge and latch-up in semiconductor devices, the disclosed system and method for extracting parasitic devices combine input data from device layout, technology rules and doping profiles in order to extract netlists, element location and substrate resistance, analyze the layout for parasitic device formation, store these lists in a verification data base, translate the data base into a specific format, and finally output lists of ESD- and latch-up-sensitive elements and their locations in a specific format such as SPICE format.Type: ApplicationFiled: February 1, 2001Publication date: October 3, 2002Inventors: Sridhar Ramaswamy, Snehamay Sinha, Gopalarao Kadamati, Ranjit Gharpurey