Patents by Inventor Snezana Jenei

Snezana Jenei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9583444
    Abstract: A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: February 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Christian Peters, Robert Allinger, Klaus Knobloch, Snezana Jenei
  • Publication number: 20150054102
    Abstract: A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.
    Type: Application
    Filed: August 20, 2013
    Publication date: February 26, 2015
    Inventors: Christian Peters, Robert Allinger, Klaus Knobloch, Snezana Jenei
  • Patent number: 8748287
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • Publication number: 20140017876
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Application
    Filed: September 13, 2013
    Publication date: January 16, 2014
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • Patent number: 8587055
    Abstract: In an embodiment, an apparatus includes a source region, a gate region and a drain region supported by a substrate, and a drift region including a plurality of vertically extending n-wells and p-wells to couple the gate region and the drain region of a transistor, wherein the plurality of n-wells and p-wells are formed in alternating longitudinal rows to form a superjunction drift region longitudinally extending between the gate region and the drain region of the transistor.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: November 19, 2013
    Assignee: Infineon Technologies AG
    Inventors: Martin Stiftinger, Snezana Jenei, Wolfgang Werner, Uwe Hodel
  • Patent number: 8536683
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 17, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • Publication number: 20130009215
    Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: Infineon Technologies AG
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Patent number: 8318553
    Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies AG
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Patent number: 8310027
    Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: November 13, 2012
    Assignee: Infineon Technologies AG
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Patent number: 8178953
    Abstract: A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 15, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Thorsten Meyer, Markus Brunnbauer, Snezana Jenei
  • Publication number: 20110201175
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Application
    Filed: March 1, 2011
    Publication date: August 18, 2011
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • Patent number: 7948064
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 24, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • Publication number: 20110095347
    Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
    Type: Application
    Filed: January 7, 2011
    Publication date: April 28, 2011
    Applicant: Infineon Technologies AG
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Patent number: 7888775
    Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: February 15, 2011
    Assignee: Infineon Technologies AG
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Publication number: 20100078779
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • Publication number: 20100078778
    Abstract: A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Hans-Joachim Barth, Thorsten Meyer, Markus Brunnbauer, Snezana Jenei
  • Publication number: 20090309167
    Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.
    Type: Application
    Filed: June 12, 2008
    Publication date: December 17, 2009
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Publication number: 20090085163
    Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Publication number: 20080203480
    Abstract: In an embodiment, an apparatus includes a source region, a gate region and a drain region supported by a substrate, and a drift region including a plurality of vertically extending n-wells and p-wells to couple the gate region and the drain region of a transistor, wherein the plurality of n-wells and p-wells are formed in alternating longitudinal rows to form a superjunction drift region longitudinally extending between the gate region and the drain region of the transistor.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 28, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Martin Stiftinger, Snezana Jenei, Wolfgang Werner, Uwe Hodel