Patents by Inventor Snorre Aunet

Snorre Aunet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7970810
    Abstract: A circuit element includes a plurality of computation blocks connected at least partially in series for processing multi-bit numbers. Each of the computation blocks includes a plurality of transistors having characteristic threshold voltages. The circuit element is configured so that the transistors will each operate at a voltage below its threshold voltage. The circuit element includes a plurality of circuit sub-elements each having an output. The circuit sub-element outputs are connected together.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: June 28, 2011
    Inventor: Snorre Aunet
  • Publication number: 20080133635
    Abstract: A circuit element includes a plurality of computation blocks connected at least partially in series for processing multi-bit numbers. Each of the computation blocks includes a plurality of transistors having characteristic threshold voltages. The circuit element is configured so that the transistors will each operate at a voltage below its threshold voltage. The circuit element includes a plurality of circuit sub-elements each having an output. The circuit sub-element outputs are connected together.
    Type: Application
    Filed: April 30, 2007
    Publication date: June 5, 2008
    Inventor: Snorre Aunet
  • Patent number: 7288968
    Abstract: A circuit element comprising N paired complementary transistors. The transistors are connected to an upper (VDD) and lower voltage level (VSS), in such a way that the paired transistors operate in subthreshold. N input terminals (X1, X2 . . . XN) are connected to the respective paired transistors. Control terminals (BP, BN) are connected to control input nodes of the transistors. The circuit element provides the possibility of real time configuration between various logic functions with a minimum of transistors and wiring.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: October 30, 2007
    Assignee: Leiv Eiriksson Nyskaping AS
    Inventor: Snorre Aunet
  • Publication number: 20070115029
    Abstract: A circuit element comprising N paired complementary transistors. The transistors are connected to an upper (VDD) and lower voltage level (VSS), in such a way that the paired transistors operate in subthreshold. N input terminals (X1, X2, . . . XN) are connected to the respective paired transistors. Control terminals (BP, BN) are connected to control input nodes of the transistors. The circuit element provides the possibility of real time configuration between various logic functions with a minimum of transistors and wiring.
    Type: Application
    Filed: December 10, 2004
    Publication date: May 24, 2007
    Inventor: Snorre Aunet