Abstract: A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.

Abstract: A semiconductor memory device including a memory array having a plurality of memory cells and a data input/output unit. A part of the memory array is assigned as a repair information region. The repair information region has a plurality of information packets. The data input/output unit reads a first and a second information packet of the plurality of information packets. The second information packet is read according to a link bit address of the first information packet.

Abstract: A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.

Abstract: A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.

Abstract: A semiconductor memory device including a memory array having a plurality of memory cells and a data input/output unit. A part of the memory array is assigned as a repair information region. The repair information region has a plurality of information packets. The data input/output unit reads a first and a second information packet of the plurality of information packets. The second information packet is read according to a link bit address of the first information packet.

Abstract: A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a second clock signal upon detecting transition of a lower bit of the start address and after the first clock signal is generated, and an address controller adapted to sequentially increment the start address in response to a transition of the second clock signal. The address controller sequentially accesses memory cells selected by the start address and the incremented start address in response to a transition of the second clock signal.