Patents by Inventor So NAGAKURA

So NAGAKURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984501
    Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: May 14, 2024
    Assignee: ROHM CO., LTD.
    Inventors: So Nagakura, Satoshi Iwahashi
  • Publication number: 20230253473
    Abstract: A method of manufacturing a semiconductor device having a super junction structure, includes: forming a first-conductivity-type semiconductor layer having a first surface and a second surface opposite to the first surface; forming a second-conductivity-type pillar region in the semiconductor layer; forming an insulating layer which covers the second surface of the semiconductor layer; forming a metal layer on the insulating layer; forming a gate electrode including a first opening passing through the metal layer by selectively removing the metal layer; and etching the insulating layer via the first opening, wherein the etching the insulating layer includes partially exposing the semiconductor layer by forming a second opening having a curved sidewall in the insulating layer by isotropic etching, and wherein an exposed surface of the semiconductor layer forms a flat surface continuous with the second surface of the semiconductor layer covered with the insulating layer.
    Type: Application
    Filed: January 5, 2023
    Publication date: August 10, 2023
    Applicant: ROHM CO., LTD.
    Inventors: So NAGAKURA, Jun KOBAYASHI, Satoshi IWAHASHI, Kazuyoshi MAKI, Shu NAKASHIMA
  • Publication number: 20230246105
    Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.
    Type: Application
    Filed: March 28, 2023
    Publication date: August 3, 2023
    Inventors: So NAGAKURA, Satoshi IWAHASHI
  • Patent number: 11646370
    Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: May 9, 2023
    Assignee: ROHM CO., LTD.
    Inventors: So Nagakura, Satoshi Iwahashi
  • Publication number: 20220069121
    Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 3, 2022
    Inventors: So NAGAKURA, Satoshi IWAHASHI
  • Patent number: 11205720
    Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 21, 2021
    Assignee: ROHM CO., LTD.
    Inventors: So Nagakura, Satoshi Iwahashi
  • Publication number: 20200381551
    Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 3, 2020
    Inventors: So NAGAKURA, Satoshi IWAHASHI