Patents by Inventor So-Ra YOU
So-Ra YOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136290Abstract: A semiconductor device having simplicity in design and improved performance and methods for fabricating the same are provided. The semiconductor device includes a substrate including a frontside and a backside opposite the frontside, an electronic device on the frontside of the substrate, an interlayer insulating layer covering the electronic device, a frontside wiring structure on the interlayer insulating layer, a backside wiring structure on the backside of the substrate, and at least one unit chain connecting the electronic device with the backside wiring structure, the unit chain including a through plug passing through the substrate, a connection contact on the interlayer insulating layer, a first chain plug passing through the interlayer insulating layer to connect the through plug with the connection contact, and a second chain plug passing through the interlayer insulating layer to be connected to the through plug.Type: ApplicationFiled: May 23, 2023Publication date: April 25, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jee Woong KIM, Jin Kyu KIM, Ho Jun KIM, Jae Hyun AHN, So Ra YOU
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Patent number: 11721581Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.Type: GrantFiled: September 24, 2020Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Chan Gwak, Hwi Chan Jun, Heon Jong Shin, So Ra You, Sang Hyun Lee, In Chan Hwang
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Publication number: 20210020509Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.Type: ApplicationFiled: September 24, 2020Publication date: January 21, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Chan GWAK, Hwi Chan JUN, Heon Jong SHIN, So Ra YOU, Sang Hyun LEE, In Chan HWANG
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Patent number: 10818549Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.Type: GrantFiled: December 23, 2019Date of Patent: October 27, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Chan Gwak, Hwi Chan Jun, Heon Jong Shin, So Ra You, Sang Hyun Lee, In Chan Hwang
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Publication number: 20200126858Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.Type: ApplicationFiled: December 23, 2019Publication date: April 23, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Chan GWAK, Hwi Chan JUN, Heon Jong SHIN, So Ra YOU, Sang Hyun LEE, In Chan HWANG
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Patent number: 10553484Abstract: A semiconductor device includes a plurality of active regions spaced apart from each other and extending linearly in parallel on a substrate. A gate electrode crosses the plurality of active regions, and respective drain regions are on and/or in respective ones of the active regions on a first side of the gate electrode and respective source regions are on and/or in respective ones of the active regions on a second side of the gate electrode. A drain plug is disposed on the drain regions and a source plug is disposed on the source regions. A gate plug is disposed on the gate electrode between the drain plug and the source plug such that a straight line passing through a center of the drain plug and a center of the source plug intersects the gate plug.Type: GrantFiled: April 23, 2018Date of Patent: February 4, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Chan Gwak, Hwi Chan Jun, Heon Jong Shin, So Ra You, Sang Hyun Lee, In Chan Hwang
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Publication number: 20190131171Abstract: A semiconductor device includes a plurality of active regions spaced apart from each other and extending linearly in parallel on a substrate. A gate electrode crosses the plurality of active regions, and respective drain regions are on and/or in respective ones of the active regions on a first side of the gate electrode and respective source regions are on and/or in respective ones of the active regions on a second side of the gate electrode. A drain plug is disposed on the drain regions and a source plug is disposed on the source regions. A gate plug is disposed on the gate electrode between the drain plug and the source plug such that a straight line passing through a center of the drain plug and a center of the source plug intersects the gate plug.Type: ApplicationFiled: April 23, 2018Publication date: May 2, 2019Inventors: Min Chan Gwak, HWI CHAN JUN, HEON JONG SHIN, SO RA YOU, SANG HYUN LEE, IN CHAN HWANG
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Patent number: 10014300Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.Type: GrantFiled: April 6, 2017Date of Patent: July 3, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Mirco Cantoro, Tae-yong Kwon, Jae-young Park, Dong-hoon Hwang, Han-ki Lee, So-ra You
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Patent number: 9966375Abstract: A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.Type: GrantFiled: February 22, 2016Date of Patent: May 8, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Joon Choi, Tae-Yong Kwon, Mirco Cantoro, Chang-Jae Yang, Dong-Hoon Khang, Woo-Ram Kim, Cheol Kim, Seung-Jin Mun, Seung-Mo Ha, Do-Hyoung Kim, Seong-Ju Kim, So-Ra You, Woong-ki Hong
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Publication number: 20170317084Abstract: An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active region may protrude from a substrate, and opposite sidewalls of the fin-type active region may be covered by an inner isolation layer. An outer isolation layer may fill an outer deep trench in the inter-device isolation region. The inner isolation layer may extend away from the device region at an inner sidewall of the outer deep trench and into the inter-device isolation region. There may be multiple fin-type active regions, and trenches therebetween. The outer deep trench and the trenches between the plurality of fin-type active regions may be of different heights. The integrated circuit device and methods of manufacturing described herein may reduce a possibility that various defects or failures may occur due to an unnecessary fin-type active region remaining around the device region.Type: ApplicationFiled: April 6, 2017Publication date: November 2, 2017Inventors: Mirco Cantoro, Tae-yong Kwon, Jae-young Park, Dong-hoon Hwang, Han-ki Lee, So-ra You
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Publication number: 20160315085Abstract: A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.Type: ApplicationFiled: February 22, 2016Publication date: October 27, 2016Inventors: Yong-Joon CHOI, Tae-Yong KWON, Mirco CANTORO, Chang-Jae YANG, Dong-Hoon KHANG, Woo-Ram KIM, Cheol KIM, Seung-Jin MUN, Seung-Mo HA, Do-Hyoung KIM, Seong-Ju KIM, So-Ra YOU, Woong-ki HONG