Patents by Inventor So Suzuki

So Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090201470
    Abstract: A projection type video display apparatus having a projection lens opening (3) formed in the front end (1a) of the apparatus and a lend adjustment opening (5) formed in one end adjacent the front end, both openings protected against dust and external mechanical shocks. The projection type video display apparatus is adapted to project an image that is generated by modulating light emitted from a light source based on video signals, through a projection lens unit (2) exposed in the projection lens opening (3). The apparatus comprises lens adjustment members (e.g. adjustment dial 4) for zooming and/or focusing the projection lens unit (2), and a cover mechanism (slide cover 7) for opening and closing the projection lens opening (3) and lend adjustment opening (5).
    Type: Application
    Filed: May 16, 2007
    Publication date: August 13, 2009
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Tatsuhiro Kurita, So Suzuki, Hiroshi Chino, Shoji Okazaki, Toshihiro Saruwatari
  • Patent number: 7566592
    Abstract: The principles described herein relate to methods for soldering electrode terminals, pins or lead-frames of commercial electric components for high temperature reliability. In one embodiment, prior to soldering the electric components, a pre-plated solder layer is removed from the lead frame or pins, and nickel and/or gold films are formed with electroless plating. The removal of the pre-plated solder layer avoids excess pre-plated Sn with high-Pb solder that lowers the melting point to between 180° C. and 220° C. and weakens solder joints. The nickel layer formed with an electroless plating acts as a barrier to the interdiffusion of tin from solder with copper of the lead frame material, which may otherwise occur at high temperatures. Interdiffusion forms an intermetallic compound layer of copper and tin and degrades solder joint strength. The novel soldering processes improve high temperature reliability of solder joints and extend electronics life-time.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: July 28, 2009
    Assignee: Schlumberger Technology Corporation
    Inventors: Shigeru Sato, Jiro Takeda, Atsushi Kayama, So Suzuki, Lionel Beneteau
  • Publication number: 20080218707
    Abstract: A projection display device accommodates, in a main body cabinet, a projection lens section to which light modulated by a light modulating element is entered, and a mirror section that reflects light transmitted through the projection lens section and directs the light to a projection plane. When the main body cabinet is mounted on a mounting plane so that the light transmitted through the projection lens section may get away from the mounting plane, a holding member which holds the main body cabinet in a upright state with regard to the mounting plane is mounted on the main body cabinet.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 11, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Takaharu Adachi, Fumihiko Hamada, So Suzuki
  • Publication number: 20080218705
    Abstract: A projection display device comprises a main body cabinet, a projection lens section to which light modulated by a light modulating element entered, and a mirror section for reflecting the light emitted from the projection lens section to a projection plane. A level difference depending on an arrangement shift of the projection lens section and the mirror section is formed on a second side surface facing a first side surface having light projection port of the main body cabinet. Furthermore, the projection display device comprises a level difference correction section for directing the light from the mirror section in a desired direction by correcting the level difference, when the main body cabinet is planed on a plane to be placed, the second side surface facing the plane to be placed.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 11, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Takaharu Adachi, Fumihiko Hamada, So Suzuki
  • Publication number: 20070212817
    Abstract: The principles described herein relate to methods for soldering electrode terminals, pins or lead-frames of commercial electric components for high temperature reliability. In one embodiment, prior to soldering the electric components, a pre-plated solder layer is removed from the lead frame or pins, and nickel and/or gold films are formed with electroless plating. The removal of the pre-plated solder layer avoids excess pre-plated Sn with high-Pb solder that lowers the melting point to between 180° C. and 220° C. and weakens solder joints. The nickel layer formed with an electroless plating acts as a barrier to the interdiffusion of tin from solder with copper of the lead frame material, which may otherwise occur at high temperatures. Interdiffusion forms an intermetallic compound layer of copper and tin and degrades solder joint strength. The novel soldering processes improve high temperature reliability of solder joints and extend electronics life-time.
    Type: Application
    Filed: October 26, 2006
    Publication date: September 13, 2007
    Applicant: Schlumberger Technology Corporation
    Inventors: Shigeru Sato, Jiro Takeda, Atsushi Kayama, So Suzuki, Lionel Beneteau
  • Patent number: 7247549
    Abstract: This invention provides a semiconductor device manufacturing method including forming a T type gate electrode having a wide region in an upper portion, the method including steps of: forming rectangular gate polysilicon; forming a nitride film covering the polysilicon; forming an oxide film thick on the nitride film; etching back the oxide film to expose the nitride film; etching the exposed nitride film, exposing the gate polysilicon, and forming a space; forming undoped polysilicon burying the space; etching back the undoped polysilicon to form a wide portion in the upper portion of the gate polysilicon; and etching the oxide film and the nitride film; siliciding the wide undoped silicon to form titanium silicide (or cobalt silicide). This manufacturing method makes it possible to easily form the T type gate electrode with good yield.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: July 24, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: So Suzuki
  • Publication number: 20060009032
    Abstract: This invention provides a semiconductor device manufacturing method including forming a T type gate electrode having a wide region in an upper portion, the method including steps of: forming rectangular gate polysilicon; forming a nitride film covering the polysilicon; forming an oxide film thick on the nitride film; etching back the oxide film to expose the nitride film; etching the exposed nitride film, exposing the gate polysilicon, and forming a space; forming undoped polysilicon burying the space; etching back the undoped polysilicon to form a wide portion in the upper portion of the gate polysilicon; and etching the oxide film and the nitride film; siliciding the wide undoped silicon to form titanium silicide (or cobalt silicide). This manufacturing method makes it possible to easily form the T type gate electrode with good yield.
    Type: Application
    Filed: September 20, 2005
    Publication date: January 12, 2006
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: So Suzuki
  • Patent number: 6979634
    Abstract: This invention provides a semiconductor device manufacturing method including forming a T type gate electrode having a wide region in an upper portion, the method including steps of: forming rectangular gate polysilicon; forming a nitride film covering the polysilicon; forming an oxide film thick on the nitride film; etching back the oxide film to expose the nitride film; etching the exposed nitride film, exposing the gate polysilicon, and forming a space; forming undoped polysilicon burying the space; etching back the undoped polysilicon to form a wide portion in the upper portion of the gate polysilicon; and etching the oxide film and the nitride film; siliciding the wide undoped silicon to form titanium suicide (or cobalt silicide). This manufacturing method makes it possible to easily form the T type gate electrode with good yield.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: December 27, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: So Suzuki
  • Patent number: 6927124
    Abstract: In a method of manufacturing a capacitor, a semiconductor substrate is provided. On the semiconductor substrate, a transistor is formed. Then, a first conductive layer is formed on the substrate. An insulating layer is formed on the first conductive layer. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned to form an upper electrode. Finally, the first conductive layer is patterned to form a lower electrode and a conductive pattern after the formation of the upper electrode.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: August 9, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: So Suzuki
  • Publication number: 20040219749
    Abstract: In a method of manufacturing a capacitor, a semiconductor substrate is provided. On the semiconductor substrate, a transistor is formed. Then, a first conductive layer is formed on the substrate. An insulating layer is formed on the first conductive layer. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned to form an upper electrode. Finally, the first conductive layer is patterned to form a lower electrode and a conductive pattern after the formation of the upper electrode.
    Type: Application
    Filed: May 28, 2004
    Publication date: November 4, 2004
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: So Suzuki
  • Patent number: 6784067
    Abstract: In a method of manufacturing a capacitor, a semiconductor substrate is provided. On the semiconductor substrate, a transistor is formed. Then, a first conductive layer is formed on the substrate. An insulating layer is formed on the first conductive layer. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned to form an upper electrode. Finally, the first conductive layer is patterned to form a lower electrode and a conductive pattern after the formation of the upper electrode.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: August 31, 2004
    Assignee: Oki Electric Industry Co, Ltd.
    Inventor: So Suzuki
  • Publication number: 20040097074
    Abstract: This invention provides a semiconductor device manufacturing method including forming a T type gate electrode having a wide region in an upper portion, the method including steps of: forming rectangular gate polysilicon; forming a nitride film covering the polysilicon; forming an oxide film thick on the nitride film; etching back the oxide film to expose the nitride film; etching the exposed nitride film, exposing the gate polysilicon, and forming a space; forming undoped polysilicon burying the space; etching back the undoped polysilicon to form a wide portion in the upper portion of the gate polysilicon; and etching the oxide film and the nitride film; siliciding the wide undoped silicon to form titanium suicide (or cobalt silicide). This manufacturing method makes it possible to easily form the T type gate electrode with good yield.
    Type: Application
    Filed: July 31, 2003
    Publication date: May 20, 2004
    Inventor: So Suzuki
  • Publication number: 20030232480
    Abstract: In a method of manufacturing a capacitor, a semiconductor substrate is provided. On the semiconductor substrate, a transistor is formed. Then, a first conductive layer is formed on the substrate. An insulating layer is formed on the first conductive layer. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned to form an upper electrode. Finally, the first conductive layer is patterned to form a lower electrode and a conductive pattern after the formation of the upper electrode.
    Type: Application
    Filed: November 26, 2002
    Publication date: December 18, 2003
    Inventor: So Suzuki
  • Patent number: D574874
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: August 12, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: So Suzuki, Yosuke Tanaka, Maki Yamauchi