Abstract: A semiconductor device having a high cutoff resistance capable of suppressing local current/electric field concentration and current concentration at a chip termination portion due to an electric field variation between IGBT cells due to a shape variation and impurity variation during manufacturing. The semiconductor device is characterized by including an emitter electrode formed on a front surface of a semiconductor substrate via an interlayer insulating film, a collector electrode formed on a back surface of the semiconductor substrate, a first semiconductor layer of a first conductivity type in contact with the collector electrode, a second semiconductor layer of a second conductivity type, a central area cell, and an outer peripheral area cell located outside the central area cell.

Abstract: The problem addressed by the present invention is to provide a semiconductor device capable of improving dv/dt controllability via a gate drive circuit during turn-on switching. The semiconductor device comprises a plurality of trench gate groups, each trench gate group including mutually adjoining three or more trench gates, and the distance between adjoining two trench gate groups is larger than the distance between adjoining two trench gates in one trench gate group. Thereby, gate-emitter capacity increases, and therefore the semiconductor device may improve dv/dt controllability via a gate drive circuit during turn-on switching.

Abstract: A semiconductor device includes first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type that is formed near a surface of the first semiconductor layer; a first main electrode that is electrically connected to the second semiconductor layer; a third semiconductor layer of the second conductivity type that neighbors the first semiconductor layer; a fourth semiconductor layer of the first conductivity type that is selectively disposed in an upper portion of the third semiconductor layer; a second main electrode that is electrically connected to the third semiconductor layer and the fourth semiconductor layer; a trench whose side face is in contact with the third semiconductor layer and the fourth semiconductor layer; a gate electrode that is formed along the side face of the trench by a sidewall of polysilicon; and a polysilicon electrode.

Abstract: A semiconductor device provides a gate electrode formed on a lateral face of a wide trench, and thereby the gate electrode is covered by a gate insulating layer and a thick insulating layer to be an inter layer. Therefore, a parasitic capacitance of the gate becomes small, and there is no potential variation of the gate since there is no floating p-layer so that a controllability of the dv/dt can be improved. In addition, the conductive layer between the gate electrodes can relax the electric field applied to the corner of the gate electrode. In consequence, compatibility of low loss and low noise and high reliability can be achieved.

Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on the first semiconductor layer; trenches in the first semiconductor layer; a semiconductor protruding part on the first semiconductor layer; a third semiconductor layer on the semiconductor protruding part; a fourth semiconductor layer on the third semiconductor layer; a gate insulating layer disposed along the trench; a first interlayer insulating layer disposed along the trench; a first conductive layer facing to the fourth semiconductor layer; a second conductive layer on the first interlayer insulating layer; a second interlayer insulating layer covering the second conductive layer; a third conductive layer on the third semiconductor layer and fourth semiconductor layer; a contacting part connecting the third conductive layer and third semiconductor layer; and a fourth conductive layer formed on the second semiconductor layer.

Abstract: A semiconductor device provides a gate electrode formed on a lateral face of a wide trench, and thereby the gate electrode is covered by a gate insulating layer and a thick insulating layer to be an inter layer. Therefore, a parasitic capacitance of the gate becomes small, and there is no potential variation of the gate since there is no floating p-layer so that a controllability of the dv/dt can be improved. In addition, the conductive layer between the gate electrodes can relax the electric field applied to the corner of the gate electrode. In consequence, compatibility of low loss and low noise and high reliability can be achieved.

Abstract: A semiconductor device provides a gate electrode formed on a lateral face of a wide trench, and thereby the gate electrode is covered by a gate insulating layer and a thick insulating layer to be an inter layer. Therefore, a parasitic capacitance of the gate becomes small, and there is no potential variation of the gate since there is no floating p-layer so that a controllability of the dv/dt can be improved. In addition, the conductive layer between the gate electrodes can relax the electric field applied to the corner of the gate electrode. In consequence, compatibility of low loss and low noise and high reliability can be achieved.

Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on the first semiconductor layer; trenches in the first semiconductor layer; a semiconductor protruding part on the first semiconductor layer; a third semiconductor layer on the semiconductor protruding part; a fourth semiconductor layer on the third semiconductor layer; a gate insulating layer disposed along the trench; a first interlayer insulating layer disposed along the trench; a first conductive layer facing to the fourth semiconductor layer; a second conductive layer on the first interlayer insulating layer; a second interlayer insulating layer covering the second conductive layer; a third conductive layer on the third semiconductor layer and fourth semiconductor layer; a contacting part connecting the third conductive layer and third semiconductor layer; and a fourth conductive layer formed on the second semiconductor layer.

Abstract: The trench IGBT is provided with a plurality of trench gates disposed in a manner so as to form wide and narrow of gaps; has a MOS structure that has a channel of a first conductivity type and that is between the trench gate pair that is disposed with a narrow gap therebetween; and is provided with a floating semiconductor layer of the first conductivity type and that is separated from the trench gates by interposing a portion of a third semiconductor layer of a second conductivity type between the trench gate pair that is disposed with a wide gap therebetween. Also, this floating semiconductor layer is disposed parallel to and at a position corresponding to an emitter electrode and a first semiconductor layer having the same electric potential, with a insulating film therebetween.

Abstract: A semiconductor device includes first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type that is formed near a surface of the first semiconductor layer; a first main electrode that is electrically connected to the second semiconductor layer; a third semiconductor layer of the second conductivity type that neighbors the first semiconductor layer; a fourth semiconductor layer of the first conductivity type that is selectively disposed in an upper portion of the third semiconductor layer; a second main electrode that is electrically connected to the third semiconductor layer and the fourth semiconductor layer; a trench whose side face is in contact with the third semiconductor layer and the fourth semiconductor layer; a gate electrode that is formed along the side face of the trench by a sidewall of polysilicon; and a polysilicon electrode.

Abstract: A semiconductor device provides a gate electrode formed on a lateral face of a wide trench, and thereby the gate electrode is covered by a gate insulating layer and a thick insulating layer to be an inter layer. Therefore, a parasitic capacitance of the gate becomes small, and there is no potential variation of the gate since there is no floating p-layer so that a controllability of the dv/dt can be improved. In addition, the conductive layer between the gate electrodes can relax the electric field applied to the corner of the gate electrode. In consequence, compatibility of low loss and low noise and high reliability can be achieved.