Patents by Inventor So-Wen Kuo

So-Wen Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6024887
    Abstract: A method for stripping an ion implanted photoresist layer from a substrate. There is first provided a substrate. There is then formed over the substrate an ion implanted photoresist layer. There is then treated the ion implated photoresist layer with a first plasma employing a first etchant gas composition comprising a fluorine containing species to form a fluorine plasma treated ion implanted photoresist layer. Finally, there is then stripped from the substrate the fluorine plasma treated ion implanted photoresist layer with a second plasma employing a second etchant gas composition comprising an oxygen containing species without the fluorine containing species. The ion implanted photoresist layer is stripped from the substrate without plasma induced damage to the substrate.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: February 15, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: So-Wen Kuo, Chin-Shan Hou, Yung Jung Chang
  • Patent number: 5981347
    Abstract: A method for forming a metal oxide semiconductor field effect transistor (MOSFET). There is first provided a semiconductor substrate. There is then formed upon the semiconductor substrate a gate dielectric layer. There is then formed upon the gate dielectric layer a gate electrode. There is then implanted into the semiconductor substrate while employing the gate electrode as a mask a pair of unactivated source/drain regions at a pair of opposite edges of the gate electrode, where the gate dielectric layer, the gate electrode and the pair of unactivated source/drain regions form an unactivated metal oxide semiconductor field effect transistor (MOSFET).
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: November 9, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: So-Wen Kuo, Lin-June Wu, Li-Huan Chu
  • Patent number: 5679214
    Abstract: A method of maintaining a strong endpoint detection signal, for RIE processes, has bean developed. After numerous RIE procedures have been performed, in a specific RIE chamber, an insitu dry cleaning procedure is implemented to remove polymer from a window in the RIE tool, a window that is used for monitoring endpoint. The insitu dry cleaning procedure is performed using oxygen or chlorine, in the etching chamber of a single wafer RIE tool, while wafers, waiting to be etched, reside in a different chamber of the single wafer RIE tool. The ability to insitu dry clean, results in little interruption in the utilization of the etching function of this tool.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: October 21, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventor: So Wen Kuo
  • Patent number: 5670426
    Abstract: A method for substantially improving the electrical characteristics of contact surfaces in contact holes and via holes that are formed in semiconductor substrates is disclosed. The method involves, in particular, the introduction of an "after-etch" process, subsequent to the application of prior art methods of "main-etch," "over-etch," and "soft-etch" that are employed in opening holes in semiconductors, in general. The said process uses an isotropic dry etch assisted by argon gas ions in such a way that the area of the contact surfaces are increased manyfold through the formation of three-dimensional structures. It is shown that the resulting electrical contact resistance of the surfaces is reduced, and therefore, improved substantially.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: September 23, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: So Wen Kuo, Chia-Shiung Tsai
  • Patent number: 5563098
    Abstract: A method of forming buried contact holes is described. A layer of silicon oxide is provided overlying a semiconductor substrate. A layer of polysilicon is deposited overlying the silicon oxide layer. The polysilicon layer is covered with a layer of photoresist which is exposed and developed to provide a photoresist mask. The polysilicon layer is etched away where it is not covered by the photoresist mask wherein a polymer buildup is formed on the sidewalls of the polysilicon layer. Ions are implanted into the silicon oxide layer not covered by the photoresist mask. The photoresist mask is removed whereby the polymer buildup is also removed. Thereafter, the silicon oxide layer not covered by the polysilicon layer is etched away to complete the formation of the buried contact hole with reduced polymer buildup in the fabrication of an integrated circuit.
    Type: Grant
    Filed: April 10, 1995
    Date of Patent: October 8, 1996
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: So-Wen Kuo, Chih-Hao Chang