Abstract: A blind display device includes a plurality of curved display panels, a support, and a plurality of rotators. Each of the curved display panels includes a curved display area between a flat display area and a bezel area. The support guides movement of the curved display panels. The rotators couple corresponding ones of the curved display panels to the support and rotate corresponding ones of the curved display panels.

Abstract: A thin-film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a first self-assembled monolayer disposed on the first gate electrode, a gate insulating layer disposed on the first self-assembled monolayer, a semiconductor disposed on the gate insulating layer, a drain electrode overlapping the semiconductor, the drain electrode being separated from and facing a source electrode with respect to the semiconductor, a first interlayer insulating layer disposed on the source electrode and the drain electrode, a second self-assembled monolayer disposed on the first interlayer insulating layer, a second gate electrode disposed on the second self-assembled monolayer, a second interlayer insulating layer disposed on the second gate electrode, and a pixel electrode disposed on the second interlayer insulating layer and connected to the drain electrode.

Abstract: A thin-film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a first self-assembled monolayer disposed on the first gate electrode, a gate insulating layer disposed on the first self-assembled monolayer, a semiconductor disposed on the gate insulating layer, a drain electrode overlapping the semiconductor, the drain electrode being separated from and facing a source electrode with respect to the semiconductor, a first interlayer insulating layer disposed on the source electrode and the drain electrode, a second self-assembled monolayer disposed on the first interlayer insulating layer, a second gate electrode disposed on the second self-assembled monolayer, a second interlayer insulating layer disposed on the second gate electrode, and a pixel electrode disposed on the second interlayer insulating layer and connected to the drain electrode.

Abstract: Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.

Abstract: A thin film transistor substrate includes a substrate, a bottom gate on the substrate, a first insulating layer on the substrate and on the bottom gate, a drain on the first insulating layer, a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain, an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source, a second insulating layer on the drain, the source, and the active layer, and a top gate on the second insulating layer.

Abstract: A thin film transistor display panel including: a first insulating substrate; a first semiconductor disposed between the first insulating substrate and a first gate insulating layer; a gate electrode disposed on the first gate insulating layer, the gate electrode overlapping the first semiconductor; a second gate insulating layer disposed on the gate electrode; a second semiconductor disposed on the second gate insulating layer, the second semiconductor overlapping the gate electrode; an interlayer insulating layer disposed on the second semiconductor; and a source electrode and a drain electrode disposed on the interlayer insulating layer spaced apart from each other, the source electrode and the drain electrode connected to the first semiconductor and the second semiconductor.

Abstract: A touch screen panel includes a substrate, a plurality of touch electrodes in a touch area of the substrate, the touch electrodes sensing a touch, a connection line connected to a touch electrode of the plurality of touch electrodes, and a pad connected to one end of the connection line. The pad includes a first pad, a second pad on the first pad within a boundary line of the first pad, and a third pad covering a top surface and a side surface of the second pad.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: The display device includes a substrate, a first gate line extending in a first direction on the substrate, a gate insulating layer formed on the substrate to cover the first gate line, a first semiconductor pattern formed on the gate insulating layer to overlap the first gate line, and including a first region and a second region, a first data line extending in a second direction that is crossing the first gate line on the gate insulating layer, and including a source electrode region that overlaps the first region of the first semiconductor pattern, a drain electrode spaced apart from the source electrode region and formed on the second region of the first semiconductor pattern, and a pixel electrode formed on the drain electrode and electrically connected to the drain electrode. The first semiconductor pattern is arranged in a third direction between the first direction and the second direction.

Abstract: A thin film transistor substrate includes a substrate, a bottom gate on the substrate, a first insulating layer on the substrate and on the bottom gate, a drain on the first insulating layer, a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain, an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source, a second insulating layer on the drain, the source, and the active layer, and a top gate on the second insulating layer.

Abstract: Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.

Abstract: Disclosed is a display substrate including a driving unit on a substrate comprising a first thin film transistor and a display unit on the substrate being adjacent to the driving unit and comprising a second thin film transistor.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.

Abstract: A thin film transistor display substrate and a method of manufacturing the same are provided. The thin film transistor substrate includes a gate electrode formed on a display substrate, an active layer formed on the gate electrode to overlap with the gate electrode and including polycrystalline silicon, a first ohmic contact layer formed on the active layer, a second ohmic contact layer formed on the first ohmic contact layer, and a source electrode and a drain electrode each formed on the second ohmic contact layer.