Patents by Inventor Sobeeh A. Almukhaizim

Sobeeh A. Almukhaizim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8006150
    Abstract: The circuit and method for increasing the scan cell observability of response compactors is based on manipulation of x distribution in responses prior to taking them through a compactor. An x-align block is capable of delaying scan chains by judiciously computed values, and thus aligning x's within the same slices. The x-alignment is effected in the insertion of proper control data to the generic x-align hardware. As a result, fewer scan cells are masked due to response x's into other cells, reflecting into enhanced test quality. An ILP formulation can be used to identify the delay assignment that leads to the maximum number of observable scan cells. Alternatively, a computationally efficient greedy heuristic can be used to attain near-optimal results in reasonable run-time. Thus, the x-align block enhances the effectiveness of response compactors and reaps high test quality, even in the dense presence of response x's.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: August 23, 2011
    Assignee: Kuwait University
    Inventors: Ozgur Sinanoglu, Sobeeh A. Almukhaizim
  • Patent number: 7937634
    Abstract: The circuit and method providing dynamic scan chain partitioning delivers peak power reduction by dynamically partitioning scan chains into multiple groups, wherein transitions are equally distributed among these multiple groups. For each test pattern, a particular partitioning that leads to the even partitioning of the transitions is computed by analyzing the transition distribution of the pattern. The scan chain partitioning is formulated using an Integer Linear Programming (ILP) and an efficient greedy heuristic. The computed information is loaded into the reconfigurable scan chain partitioning hardware during the capture window. The partitioning hardware is composed of controllable clock gating logic, which is reconfigured on a per pattern basis, wherein the reconfiguration is effected by only utilizing the existing scan channels. The reconfigurability delivers a solution that is test set independent.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: May 3, 2011
    Inventors: Sobeeh A. Almukhaizim, Ozgur Sinanoglu
  • Publication number: 20100218061
    Abstract: The circuit and method for increasing the scan cell observability of response compactors is based on manipulation of x distribution in responses prior to taking them through a compactor. An x-align block is capable of delaying scan chains by judiciously computed values, and thus aligning x's within the same slices. The x-alignment is effected in the insertion of proper control data to the generic x-align hardware. As a result, fewer scan cells are masked due to response x's into other cells, reflecting into enhanced test quality. An ILP formulation can be used to identify the delay assignment that leads to the maximum number of observable scan cells. Alternatively, a computationally efficient greedy heuristic can be used to attain near-optimal results in reasonable run-time. Thus, the x-align block enhances the effectiveness of response compactors and reaps high test quality, even in the dense presence of response x's.
    Type: Application
    Filed: February 24, 2009
    Publication date: August 26, 2010
    Inventors: Ozgur Sinanoglu, Sobeeh A. Almukhaizim
  • Publication number: 20100211839
    Abstract: The circuit and method providing dynamic scan chain partitioning delivers peak power reduction by dynamically partitioning scan chains into multiple groups, wherein transitions are equally distributed among these multiple groups. For each test pattern, a particular partitioning that leads to the even partitioning of the transitions is computed by analyzing the transition distribution of the pattern. The scan chain partitioning is formulated using an Integer Linear Programming (ILP) and an efficient greedy heuristic. The computed information is loaded into the reconfigurable scan chain partitioning hardware during the capture window. The partitioning hardware is composed of controllable clock gating logic, which is reconfigured on a per pattern basis, wherein the reconfiguration is effected by only utilizing the existing scan channels. The reconfigurability delivers a solution that is test set independent.
    Type: Application
    Filed: February 17, 2009
    Publication date: August 19, 2010
    Inventors: Sobeeh A. Almukhaizim, Ozgur Sinanoglu