Patents by Inventor Soe Myint

Soe Myint has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9853916
    Abstract: Described is an apparatus comprising one or more router circuitries. One or more of the circuitries may be a shared-bus router circuitry including a plurality of shared-bus ports and a shared-bus datapath, and one or more of the circuitries may be a crossbar router circuitry including a plurality of crossbar ports and a crossbar datapath. Also described are methods of making the apparatus, which may include: providing one or more design files modeling the apparatus, the shared-bus datapath, and the crossbar datapath; incorporating a configuration parameter for the datapath into the one or more design files; and setting an RTL configuration parameter to instantiate either the shared-bus backbone or the crossbar backbone. The methods may also include loading the one or more design files with a design tool and compiling the one or more design files with the design tool.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 26, 2017
    Assignee: Intel Corporation
    Inventors: Robert P. Adler, Cristian E. Savin, Vishnu Vardhan Nandakumar, Yashpreet Kaur, Soe Myint
  • Publication number: 20170289063
    Abstract: Described is an apparatus comprising one or more router circuitries. One or more of the circuitries may be a shared-bus router circuitry including a plurality of shared-bus ports and a shared-bus datapath, and one or more of the circuitries may be a crossbar router circuitry including a plurality of crossbar ports and a crossbar datapath. Also described are methods of making the apparatus, which may include: providing one or more design files modeling the apparatus, the shared-bus datapath, and the crossbar datapath; incorporating a configuration parameter for the datapath into the one or more design files; and setting an RTL configuration parameter to instantiate either the shared-bus backbone or the crossbar backbone. The methods may also include loading the one or more design files with a design tool and compiling the one or more design files with the design tool.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Robert P. Adler, Cristian E. Savin, Vishnu Vardhan Nandakumar, Yashpreet Kaur, Soe Myint
  • Patent number: 9069699
    Abstract: Methods and apparatuses are described for identifying inconsistent constraints. During operation, a system can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. If an inconsistency or conflict is detected while solving the set of constraints, the system can identify a phase in a series of phases of the constraint solver where the inconsistency was detected. The system can then try to solve different subsets of the set of constraints to identify smaller subsets of the set of constraints that contain the inconsistency. When the system tries to solve a subset of the set of constraints, the system can determine whether or not an inconsistency is detected in the identified phase while solving the subset of the set of constraints. Next, the system can report the smallest subset of inconsistent constraints that was found to a user.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: June 30, 2015
    Assignee: SYNOPSYS, INC.
    Inventors: Dhiraj Goswami, Soe Myint, Ngai Ngai William Hung, Rajarshi Mukherjee
  • Publication number: 20120253754
    Abstract: Methods and apparatuses are described for identifying inconsistent constraints. During operation, a system can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. If an inconsistency or conflict is detected while solving the set of constraints, the system can identify a phase in a series of phases of the constraint solver where the inconsistency was detected. The system can then try to solve different subsets of the set of constraints to identify smaller subsets of the set of constraints that contain the inconsistency. When the system tries to solve a subset of the set of constraints, the system can determine whether or not an inconsistency is detected in the identified phase while solving the subset of the set of constraints. Next, the system can report the smallest subset of inconsistent constraints that was found to a user.
    Type: Application
    Filed: March 29, 2011
    Publication date: October 4, 2012
    Applicant: SYNOPSYS, INC.
    Inventors: Dhiraj Goswami, Soe Myint, Ngai Ngai William Hung, Rajarshi Mukherjee
  • Patent number: 7895552
    Abstract: In the field of functional verification of digital designs in systems that use an abstraction for portions of a circuit design to perform the verification proof, a tool is described for resolving inconsistencies between the design and abstractions for the design. The tool provides information to a user about intermediate steps in the verification process. In response, the user may provide insight about the design to allow the tool to adjust the verification analysis of the design. The information provided to the user, including possible conflicts between the design and its abstractions, may include visualization techniques to facilitate the user's understating of any inconsistencies.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: February 22, 2011
    Assignee: Jasper Design Automation, Inc.
    Inventors: Vigyan Singhal, Soe Myint, Chung-Wah Norris Ip, Howard Wong-Toi
  • Patent number: 7437694
    Abstract: A system and method for identifying, for a selected signal, those signals whose value is relevantly determined based upon a value of the selected signal, where a set of signals to be examined is identified as those signals that satisfy one or more of the following criteria: (1) they are RTL load signals of the selected signal, (2) they are RTL load signals that are also in an analysis region, (3) they are RTL load signals within the analysis region that also contribute to a proof target, and/or 4) they are RTL load signals that contribute to the proof target.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: October 14, 2008
    Assignee: Jasper Design Automation
    Inventors: Lawrence Loh, Chung-Wah Norris Ip, Soe Myint
  • Patent number: 7159198
    Abstract: The present invention is directed to a system and a method for verifying properties of a circuit model while providing information to help the user manually modify a design analysis region and/or environmental constraints. While conventional systems attempt to substantially automate the entire formal verification process, the present invention iteratively provides information to the user about the cost and effect of changes to the environmental constraints and the analysis region. This information enables the user to weigh the effectiveness and efficiency of one or more modifications to the design analysis area and/or to the environmental constraints (assumptions). The information provided to the user can help a user compare a variety of alternative modifications in order to select the modifications that are efficient and effective.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: January 2, 2007
    Assignee: Jasper Design Automation
    Inventors: Chung-Wah Norris Ip, Lawrence Loh, Vigyan Singhal, Howard Wong-Toi, Soe Myint
  • Patent number: 6059470
    Abstract: There is provided an adjustable, curved keyboard having arcuately arranged keys to complement naturally to a user's wrists, hands and fingers. The keyboard is supported by a bracket, which extends from underneath the desktop of a desk, for pivotal, elevational and horizontal adjustment of the keyboard's position relative to the user. The keyboard comprises an elongated base and alphanumeric keys positioned at an upper surface of the base. The base has a longitudinal axis disposed below the upper surface of the elongated base, and the upper surface is curved about the longitudinal axis. Also, the alphanumeric keys are arranged about the longitudinal axis of the base to form an arcuate typing surface that provides a comfortable typing surface for the user and reduces the risks of repetitive stress injury.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: May 9, 2000
    Inventor: Soe Myint
  • Patent number: 5735619
    Abstract: There is provided an adjustable, curved keyboard having arcuately arranged keys to complement naturally to a user's wrists, hands and fingers. The keyboard is supported by a bracket, which extends from underneath the desktop of a desk, for pivotal, elevational and horizontal adjustment of the keyboard's position relative to the user. The keyboard comprises an elongated base and alphanumeric keys positioned at an upper surface of the base. The base has a longitudinal axis disposed below the upper surface of the elongated base, and the upper surface is curved about the longitudinal axis. Also, the alphanumeric keys are arranged about the longitudinal axis of the base to form an arcuate typing surface that provides a comfortable typing surface for the user and reduces the risks of repetitive stress injury.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: April 7, 1998
    Inventor: Soe Myint