Abstract: This control circuit adjusts two signal waveforms to a phase difference of exactly 90.degree. and to exactly equal amplitudes of the respective frequency components. It is a digital circuit containing a phase control stage (pr) and an amplitude control stage (ar). The control circuit (r) delivers first and second quadrature signals (q1, q2) which are multiplied together to obtain a phase control value (p) which is multiplied by one of the digitized quadrature analog signals and added vectorially to the second digital signal. The two signals thus brought to a phase difference of exactly 90.degree. are the two phase-corrected digital signals (p1, p2). In the amplitude control stage (ar), one of the two phase-corrected digital signals (p2, p1) is multiplied by the amplitude control value (g) from the amplitude comparator (av1, av2), and the product is the amplitude- and phase-corrected quadrature signal (q2, q1) belonging to the other quadrature signal (q1, q2).

Abstract: A monolithic integrated digital-to-analog converter makes use of rotating current-source control (dynamic element matching). After the conversion of a digital input signal into a code containing a sequence of first binary conditions corresponding to the numerical value of the input signal (so-called thermometer code), the bit switches of possibly same-sized current sources are rotatingly controlled in the sense of being selected, so that it becomes possible in the manufacture of the monolithic integrated digital-to-analog converters to balance out the manufacturing tolerances or process variations of the current sources.

Abstract: A digital delay arrangement generates a delay time which is a noninteger multiple of the period of a system clock frequency. The arrangement includes a digital delay circuit having a delay time equal to the period, a multiplier for the part of the noninteger multiplier, b, being less than one, a further multiplier for 1- b, an adder and a peaking filter clocked by the system clock.

Abstract: To raise the integration level of a video recorder, and to provide a uniform circuit concept suitable for all three color-television standard (PAL, NTSC, SECAM) which, in particular, requires only slight modifications for adaptation to the respective standard, signal processing is performed by fast digital circuits whose signals are stored on the recording medium not in digital form, but after digital-to-analog conversion. The composite color signal is converted into digital form by a fast analog-to-digital converter (aw) whose sampling signal (fc) has a fixed frequency (Fc) for all three color-television standards. Digital signal processing in the chroma channel is performed at a fixed subcarrier frequency (zt) for all three color-television standards which is an integral subharmonic of the sampling frequency (Fc).

Abstract: The frequency of a signal is classified in at least two nonoverlapping frequency ranges using the variable frequency of a clock signal as a reference. The clock signal is applied to the count input of a first up counter, and the signal to the reset input of this up counter and to the enable input of a first buffer. The parallel inputs of the first buffer are connected to the count outputs of the up counter, and the parallel outputs of this buffer are coupled to the parallel inputs of a multiple comparator in which each nonoverlapping frequency range is assigned a digital output. Each of these digital outputs is connected to the D input of a D flip-flop, which is clocked by the signal, and to one of the two inputs of an EXOR gate having its other input connected to the Q output of the associated flip-flop.

Abstract: The circuit arrangement includes a basic circuit for calculating the zeroth approximation and expandable by at least one correction circuit for calculating a first or further approximations. The basic circuit contains a first adder, a second adder, a first constant multiplier, a second constant multiplier, a first absolute-value stage, a second absolute-value stage and a third absolute-value stage which is interposed between a subtracter and the input of the second constant multiplier. The output of the second constant multiplier is coupled to one input of the second adder, whose output provides the zeroth approximation to the value of the complex digital quantity. Each of the two input signals is fed through one of the absolute-value stages to one of the two inputs of the subtracter and the first adder.

Abstract: The output signal of one tuner or of other TV signal sources in the base band are digitized and stored in a part of a memory. After automatic switching over to another TV-channel, this new signal is stored in another part of the memory and so on. The whole memory is then read out continuously and produces the displayed multipicture on the screen.

Abstract: To determine the phase difference between the edge of a pulse of a first clock signal and the edge of a pulse of a second clock signal with an integrable phase meter circuit, the second clock signal is fed through a frequency-divider circuit to the input of an unclocked delay line including m delay elements, and to a second register containing m cells, while the m cells of a first register are clocked by the first clock signal. The outputs of the kth register cells are compared in the kth XOR gate of a row of m XOR gates, so that, when the levels of these outputs are unlike, a logic 1 appears at the output of the kth gate. The phase is obtained at the n-bit output of a multiple adder adding the logic levels, the accuracy corresponding to m, which is preferably equal to 2.sup.n.

Abstract: In this circuit, the subcircuits substantially contributing to the computation time of the time-critical loop are only a subtracter, a quantizer and a delay element. The digital video signals whose number of bits is to be reduced can thus have clock rates of 17 to 20 MHz if the circuit is implemented using CMOS or N-channel MOS technology.

Abstract: A digital television receiver circuit filters and demodulates a signal contained in the input signal of the television receiver and frequency-modulated with at least one audio signal. The only A/D converter required in the circuit is the converter for changing the video signal from analog to digital form. The circuit uses digital filters, a digital mixer, decimation stages and a digital frequency demodulator stage to separate the audio signal from the composite video signal.

Abstract: In a frequency synthesizer circuit, a phase-locked loop serves to generate an analog signal. The circuit includes a phase comparator, a reference oscillator, an analog low-pass filter, and a voltage-controlled oscillator (VCO). The output of the VCO is the analog signal. The phase comparator is a digital circuit to which the two phases to be compared are furnished as digital signals. One of the phase signals is a signal representative of the phase of the reference oscillator. The second phase signal is derived from an accumulator which is clocked by the VCO and accumulates an adjustable numerical value on receipt of each clock pulse. The content of the accumulator is fed to the phase comparator as the second phase signal. The phase-locked loop synchronizes the accumulator cycle frequency, which is adjustable via the numerical value, with the reference or VCO frequency and thus determines the frequency of the analog signal.

Abstract: An interface circuit is provided which permits a color-television receiver with digital signal-processing circuitry which reproduces the video signal at twice the horizontal frequency to be connected to a home computer whose clock-signal system is not synchronized with that of the color-television receiver. For each color character signal, the interface circuit contains two digital delay lines, one data register, two code converters, one line memory, and one multiple switch.

Abstract: A divider-by-factor frequency divider circuit is described. The rate-multiplier principle of eliminating pulses as regularly as possible from a number of pulses of the signal to be frequency-divided is modified so that low-frequency variations in the frequency-divided signal are reduced at the expense of an increase in higher-frequency variations. This modification is achieved through the addition of a second accumulator, a pair of adders, a subtracter and a presettable counter to the accumulator of a frequency divider circuit. A rate multiplier with a coloring characteristic inverse to pink noise is thereby obtained.

Abstract: A high definition TV receiver includes a single frame memory arranged with three memory areas, three multiplexers, a movement detector, a half image interpolator and a control circuit to provide flicker-free video reproduction.

Abstract: A subcircuit for the demodulation of SECAM color-television signals has two signal paths each including a low-pass filter (tp1, tp2) which has the transfer function H(z)=(1+ z.sup.-1).sup.5. The amount of area required by the subcircuit on an integrated-circuit chip is thus kept small.

Abstract: A digital signal derived from an analog signal by means of an analog-to-digital converter clocked by a clock signal is fed to a first delay element and a 90.degree. phase shifter at the same time. The delayed digital signal is applied through a second delay element to one input of a first multiplier and directly to the other input of this multiplier. In similar fashion, the signal at the output of the 90.degree. phase shifter is applied directly to one input of a second multiplier and through a third delay element to the other input of this multiplier. The output signals of the multipliers are combined in an adder to provide the demodulated digital signal. In accordance with the invention, multiple multiplications and a signal mixture to form the Hilbert-transformed signal, which are necessary in the known prior art, can be avoided.

Abstract: A digital phase detector for processing digital signals consisting of words containing more than 10 bits eliminates the need for a large read-only memory for arc tan values and requires only individual read-only memories for the arc tan values 2.sup.-r, where r=1 . . . n. n-1 like stages are provided each of which consists of an adder, a subtracter, two constant multipliers for the factor 2.sup.-r, and three changeover switches. The nth stage contains a constant multiplier for 2.sup.-n, a subtracter, and a changeover switch. The outputs of one of the changeover switches in each of the like stages and of the changeover switch in the nth stage are coupled to the inputs of a multiple-input adder whose output provides the phase detected digital signal. In a second variant of the solution, only j stages contain the above-mentioned subcircuits, while the other stages are simplified to form cells each of which contains only one constant multiplier, a subtracter with associated changeover switch, and an inverter.