Patents by Inventor Soenke Ostertun
Soenke Ostertun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941281Abstract: A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, reading a first value of the first memory cell, reading a second value of the second memory cell, and determining the value of the memory flag based on the first value and the second value. In embodiments, the memory flag may have more than 2-bits.Type: GrantFiled: April 1, 2022Date of Patent: March 26, 2024Assignee: NXP B.V.Inventor: Soenke Ostertun
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Publication number: 20230315325Abstract: A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, reading a first value of the first memory cell, reading a second value of the second memory cell, and determining the value of the memory flag based on the first value and the second value. In embodiments, the memory flag may have more than 2-bits.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Inventor: Soenke Ostertun
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Publication number: 20230274787Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.Type: ApplicationFiled: May 8, 2023Publication date: August 31, 2023Inventors: Soenke Ostertun, Björn Fay, Vitaly Ocheretny
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Patent number: 11694761Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.Type: GrantFiled: September 17, 2021Date of Patent: July 4, 2023Assignee: NXP B.V.Inventors: Soenke Ostertun, Bjorn Fay, Vitaly Ocheretny
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Publication number: 20230089443Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.Type: ApplicationFiled: September 17, 2021Publication date: March 23, 2023Inventors: Soenke Ostertun, Bjorn Fay, Vitaly Ocheretny
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Patent number: 10657294Abstract: In accordance with a first aspect of the present disclosure, a non-volatile memory is provided, comprising: a plurality of storage elements; a plurality of access transistors, said access transistors being connected to one or more of said storage elements; a measurement unit, wherein said measurement unit is configured to measure a variation between electrical characteristics of said access transistors; a processing unit configured to use said variation between electric characteristics as a physical unclonable function. In accordance with a second aspect of the present disclosure, a corresponding method of manufacturing a non-volatile memory is conceived.Type: GrantFiled: September 25, 2019Date of Patent: May 19, 2020Assignee: NXP B.V.Inventors: Christoph Hans Joachim Garbe, Soenke Ostertun
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Publication number: 20200117836Abstract: In accordance with a first aspect of the present disclosure, a non-volatile memory is provided, comprising: a plurality of storage elements; a plurality of access transistors, said access transistors being connected to one or more of said storage elements; a measurement unit, wherein said measurement unit is configured to measure a variation between electrical characteristics of said access transistors; a processing unit configured to use said variation between electric characteristics as a physical unclonable function. In accordance with a second aspect of the present disclosure, a corresponding method of manufacturing a non-volatile memory is conceived.Type: ApplicationFiled: September 25, 2019Publication date: April 16, 2020Inventors: CHRISTOPH HANS JOACHIM GARBE, Soenke Ostertun
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Patent number: 9983820Abstract: In an embodiment, a method for re-programming memory is disclosed. In the embodiment, the method involves selecting a memory page based on version information and re-programming the selected memory page using cyclic redundancy check (CRC) data for the memory page.Type: GrantFiled: March 29, 2016Date of Patent: May 29, 2018Assignee: NXP B.V.Inventors: Sönke Ostertun, Wolfgang Stidl, Raffaele Costa
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Patent number: 9866206Abstract: There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply tType: GrantFiled: June 17, 2016Date of Patent: January 9, 2018Assignee: NXP B.V.Inventors: Maurits Storms, Soenke Ostertun, Frantisek Cevela
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Publication number: 20170285996Abstract: In an embodiment, a method for re-programming memory is disclosed. In the embodiment, the method involves selecting a memory page based on version information and re-programming the selected memory page using cyclic redundancy check (CRC) data for the memory page.Type: ApplicationFiled: March 29, 2016Publication date: October 5, 2017Applicant: NXP B.V.Inventors: SÖNKE OSTERTUN, Wolfgang STIDL, Raffaele COSTA
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Publication number: 20160373092Abstract: There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (N11, N12), a second switching element (N13), a first voltage supply tType: ApplicationFiled: June 17, 2016Publication date: December 22, 2016Inventors: Maurits Storms, Soenke Ostertun, Frantisek Cevela
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Patent number: 9509306Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.Type: GrantFiled: April 19, 2013Date of Patent: November 29, 2016Assignee: NXP B.V.Inventors: Soenke Ostertun, Michael Ziesmann
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Patent number: 9471792Abstract: There is provided a detection arrangement for detecting an attack to internal signals in a semiconductor device. The detection arrangement comprises a first input terminal, a second input terminal, and a comparison unit. The first input terminal is adapted to receive a first signal being indicative for a signal at a first stage of a driver of the semiconductor device, the driver being capable to drive signals internally to the semiconductor device. The second input terminal is adapted to receive a second signal being indicative for a signal at a second stage of the driver of the semiconductor device. The comparison unit is adapted to compare the first signal and the second signal and to determine a time period during which the signals are equal, wherein the determined time period is indicative for a potential attack, if the determined time period is above a predefined threshold.Type: GrantFiled: August 26, 2013Date of Patent: October 18, 2016Assignee: NXP B.V.Inventors: Soenke Ostertun, Joachim Christoph Hans Garbe
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Patent number: 9454471Abstract: An electronic counter is provided having a sequence of memory cells and increment logic. Each memory cell of the sequence is non-volatile and supports a one state and a zero state. The one state can also be referred to as a ‘programmed state’, the zero state as an ‘erased state’. The counter is configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter.Type: GrantFiled: September 17, 2013Date of Patent: September 27, 2016Assignee: NXP B.V.Inventors: Martin Feldhofer, Franz Amtmann, Soenke Ostertun, Alicia da Conceicao
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Publication number: 20140089612Abstract: An electronic counter comprising a sequence of memory cells, each memory cell being non-volatile and supporting a one state and a zero state, the counter being configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter, the increment logic comprising programming increment logic and erasing increment logic, the increment logic being configured to alternate between a programming phase in which the programming increment logic advances the pattern, and an erasing phase in which the erasing increment logic advances the pattern, wherein the programming increment logic is configured to program a next cell of the sequence of non-volatile memory cells from a zero state to a one state, the program phase terminating when all memory cells of the sequence of memory cells are iType: ApplicationFiled: September 17, 2013Publication date: March 27, 2014Applicant: NXP B.V.Inventors: Martin Feldhofer, Franz Amtmann, Soenke Ostertun, Alicia da Conceicao
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Publication number: 20140068762Abstract: There is provided a detection arrangement for detecting an attack to internal signals in a semiconductor device. The detection arrangement comprises a first input terminal, a second input terminal, and a comparison unit. The first input terminal is adapted to receive a first signal being indicative for a signal at a first stage of a driver of the semiconductor device, the driver being capable to drive signals internally to the semiconductor device. The second input terminal is adapted to receive a second signal being indicative for a signal at a second stage of the driver of the semiconductor device. The comparison unit is adapted to compare the first signal and the second signal and to determine a time period during which the signals are equal, wherein the determined time period is indicative for a potential attack, if the determined time period is above a predefined threshold.Type: ApplicationFiled: August 26, 2013Publication date: March 6, 2014Applicant: NXP B.V.Inventors: Soenke Ostertun, Joachim Christoph Hans Garbe
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Publication number: 20130307578Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.Type: ApplicationFiled: April 19, 2013Publication date: November 21, 2013Applicant: NXP B.V.Inventors: Soenke Ostertun, Michael Ziesmann
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Patent number: 8284608Abstract: A non-volatile memory circuit includes memory rows and supporting circuits coupled to the memory rows, where at least one of the memory rows include at least one Electrically Erasable Programmable Read-Only Memory (EEPROM) memory element and at least one Flash memory element. The EEPROM and Flash elements are configured to share some of the supporting circuits and can be accessed in parallel.Type: GrantFiled: October 5, 2010Date of Patent: October 9, 2012Assignee: NXP B.V.Inventors: Sönke Ostertun, Christoph Hans Joachim Garbe, Andreas Nentwig, Nils Sandersfeld
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Publication number: 20120081966Abstract: A non-volatile memory circuit includes memory rows and supporting circuits coupled to the memory rows, where at least one of the memory rows include at least one Electrically Erasable Programmable Read-Only Memory (EEPROM) memory element and at least one Flash memory element. The EEPROM and Flash elements are configured to share some of the supporting circuits and can be accessed in parallel.Type: ApplicationFiled: October 5, 2010Publication date: April 5, 2012Applicant: NXP B.V.Inventors: Sönke OSTERTUN, CHRISTOPH HANS JOACHIM GARBE, ANDREAS NENTWIG, NILS SANDERSFELD
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Patent number: 8102725Abstract: A method of controlling a pre-charge process of a data line (21, 22) in an integrated circuit (100) comprises the step of monitoring a rate of change of a voltage applied to the data line (21, 22) for enhancing the security. Further a respective integrated circuit (100) is disclosed.Type: GrantFiled: August 20, 2008Date of Patent: January 24, 2012Assignee: NXP B.V.Inventor: Soenke Ostertun