Abstract: A system is provided for facilitating an enhanced video pipeline in order to improve color perception. The system comprises a first source configured to generate a first video stream, a second source configured to generate a second video stream, and a computing device. In this context, the computing device is configured to superpose the first video stream onto the second video stream, thereby generating an output video stream. The computing device is further configured to calculate weighting factors for individual pixels or discrete pixel sets of adjacent individual pixels of the output video stream by analyzing the first video stream and/or the second video stream.

Abstract: A display system is provided that comprises a display panel having a plurality of pixel arrangement. Each pixel arrangement comprises at least one light emitting unit, at least one driver circuit operably coupled to the light emitting unit, and at least one digital counter operably coupled to the driver circuit. In this regard, the digital counter is configured to store a data value to be counted and to toggle a state of the driver circuit upon expiry, thereby toggling a state of the light emitting unit to perform luminance control of the pixel arrangement.

Abstract: A circuitry (30) for on-chip power regulation is provided. The circuitry (30) comprises a memory array (31) comprising a plurality of memory cell blocks (32) arranged in rows and columns, where the memory cell blocks are clustered into a defined number of memory cell blocks (33) along the row, each cluster (33) is connected to a respective local reference line (34). In addition, the circuitry (30) comprises a plurality of sense amplifiers (40) connected to the respective memory cell blocks (32). The circuitry (30) further comprises at least one dummy memory cell block (35) additionally arranged to each cluster of memory cell blocks (33), where the dummy memory cell block (35) is connected to a main reference line (36). Moreover, the circuitry (30) comprises at least one transistor (37) arranged in between the local reference line (34) of each cluster of memory cell blocks (33) and the main reference line (36).

Abstract: A display system includes a first die configured to emit light of a first color, a second die configured to emit light of a second color and a third die configured to emit light of a third color. The display system also includes a lens system and an optical waveguide system. The optical waveguide system includes a first grating portion configured to couple in an incident light to the optical waveguide and a second grating portion configured to couple out a transmitting light from the optical waveguide. The first die, the second die and the third die are contained in one package. The lens system is arranged between the package and the optical waveguide system, and is configured to collimate the light of the first color, the light of the second color and the light of the third color onto the first grating portion of the optical waveguide system.

Abstract: A method is provided to produce dies for a wafer reconstitution. The method comprises steps of inspecting an epitaxial wafer to detect one or more defects, overlaying a dicing scheme on the epitaxial wafer with the detected defects, classifying the dies in the dicing scheme as good dies or bad dies, and dicing the good dies and transferring the good dies onto a carrier wafer or a target wafer to wafer reconstitution.

Abstract: A method is provided for optimizing beam shaping of a display comprising an array of light emitting elements, each corresponds to a pixel of said display, in order to adjust angular distribution of light pattern in an optical waveguide. The method comprises the step of simulating a luminance distribution for positional and angular characteristics of luminance of the optical waveguide. The method further comprises the step of measuring a luminance distribution for positional and angular characteristics of luminance of the optical waveguide. The method further comprises the step of comparing the simulated luminance distribution with the measured luminance distribution of the optical waveguide. In addition, the method further comprises the step of defining an optimum emission pattern for every pixel for every color of the display based on the simulated and measured luminance distribution.

Abstract: A system is provided for facilitating an enhanced video pipeline in order to improve color perception. The system comprises a first source configured to generate a first video stream, a second source configured to generate a second video stream, and a computing device. In this context, the computing device is configured to superpose the first video stream onto the second video stream, thereby generating an output video stream. The computing device is further configured to calculate weighting factors for individual pixels or discrete pixel sets of adjacent individual pixels of the output video stream by analyzing the first video stream and/or the second video stream.

Abstract: An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (?LED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts.

Abstract: Example embodiments relate to monolithically integrated antenna devices. One embodiment includes a monolithically integrated antenna device that includes a substrate having a first surface and a second surface. The monolithically integrated antenna device also includes a transistor component layer that includes at least one electronic component therein. Further, the monolithically integrated antenna device includes at least one antenna structure formed on the substrate or the transistor component layer. The antenna structure is configured to operate in a frequency range of between 30 kHz and 2.4 GHz. The substrate is configured to have a size that is the same or larger than the at least one antenna structure. The at least one antenna structure is formed in a stack with the transistor component layer and the substrate. The monolithically integrated antenna device is configured to shield the at least one electronic component in the transistor component layer from electromagnetic interference.

Abstract: An example includes sensing radiation with a photo diode; storing, in a pixel capacitor electrically coupled to the photo diode, electric charge supplied by the photo diode in response to the sensed radiation; providing a pixel amplifier output signal at an output link of a pixel amplifier having an input link electrically coupled to the pixel capacitor, where the pixel amplifier output signal depends on an amount of the electric charge stored in the capacitor; providing, to analyzing circuitry of the image sensor apparatus, a pixel output signal at a pixel output link of the radiation sensing pixel element by a pixel selector transistor, the pixel output signal being dependent on the pixel amplifier output signal and a selector control signal provided by the analyzing circuitry; and controlling a gain defining a dependency between the pixel output signal and the amount of the electric charge stored in the capacitor.

Abstract: A method is provided for obtaining one or more Light Emitting Diode (LED) devices reconstituted over a carrier substrate. The method includes providing a silicon-based semiconductor substrate as the carrier substrate; providing, per each of the one or more LED devices, a compound semiconductor stack including an LED layer; applying a SiCN layer to the stack and the substrate, respectively; bonding the stack to the substrate, wherein the SiCN layer applied to the stack and the SiCN layer applied to the substrate are contacted; and annealing, after bonding, the bonded stack and substrate at a temperature equal to or higher than a processing temperature for completing the LED device from the stack, wherein said temperatures are at least 400° C. A semiconductor structure including the one or more LED devices reconstituted over a carrier substrate is also provided.

Abstract: A Light Emitting Diode (LED) device, particularly a micro-LED (?LED) device, suitable for a ?LED display is described. The LED device comprises a LED array with a plurality of LEDs 12. It also comprises at least one top contact and bottom contact electrically connected to the LED array. Further, it comprises a conductive structure arranged above the LED array and the top contact, respectively, and electrically connected to the top contact. The conductive structure is, regarding each LED of the LED array, configured to absorb a first part of the light emitted by the LED, and to pass a second part of the light emitted by the LED. An emission angle (beam angle) of the passed light is thereby smaller than an emission angle of the light emitted by the LED.

Abstract: Example embodiments relate to monolithically integrated antenna devices. One embodiment includes a monolithically integrated antenna device that includes a substrate having a first surface and a second surface. The monolithically integrated antenna device also includes a transistor component layer that includes at least one electronic component therein. Further, the monolithically integrated antenna device includes at least one antenna structure formed on the substrate or the transistor component layer. The antenna structure is configured to operate in a frequency range of between 30 kHz and 2.4 GHz. The substrate is configured to have a size that is the same or larger than the at least one antenna structure. The at least one antenna structure is formed in a stack with the transistor component layer and the substrate. The monolithically integrated antenna device is configured to shield the at least one electronic component in the transistor component layer from electromagnetic interference.

Abstract: A display of an active matrix thin film emitter LED type is provided, including a substrate, a plurality of pixels of a thin film emitter LED type arranged separated from each other on the substrate, a plurality of thin film photodetectors arranged between the pixels, an encapsulation layer covering the pixels and photodetectors, one or more diaphragms of a visible-light-absorbing material, provided on the encapsulation layer and including a plurality of apertures each centered over a respective one of the photodetectors, and at least one cover layer transparent to visible light and provided on the encapsulation layer and the one or more diaphragms. Methods of operating and manufacturing of such a display are also provided.

Abstract: A method is provided for obtaining one or more Light Emitting Diode (LED) devices reconstituted over a carrier substrate. The method includes providing a silicon-based semiconductor substrate as the carrier substrate; providing, per each of the one or more LED devices, a compound semiconductor stack including an LED layer; applying a SiCN layer to the stack and the substrate, respectively; bonding the stack to the substrate, wherein the SiCN layer applied to the stack and the SiCN layer applied to the substrate are contacted; and annealing, after bonding, the bonded stack and substrate at a temperature equal to or higher than a processing temperature for completing the LED device from the stack, wherein said temperatures are at least 400° C. A semiconductor structure including the one or more LED devices reconstituted over a carrier substrate is also provided.

Abstract: A Light Emitting Diode (LED) device, particularly a micro-LED (?LED) device, suitable for a ?LED display is described. The LED device comprises a LED array with a plurality of LEDs 12. It also comprises at least one top contact and bottom contact electrically connected to the LED array. Further, it comprises a conductive structure arranged above the LED array and the top contact, respectively, and electrically connected to the top contact. The conductive structure is, regarding each LED of the LED array, configured to absorb a first part of the light emitted by the LED, and to pass a second part of the light emitted by the LED. An emission angle (beam angle) of the passed light is thereby smaller than an emission angle of the light emitted by the LED.

Abstract: An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (?LED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts.

Abstract: An integrated circuit device comprising a power control unit for controlling the power of a power isle is disclosed. The power control unit comprises (i) a power gating switch implemented in the BEOL portion for switching ON/OFF the power to the power isle, (ii) a state recovery circuit comprising a memory element in the FEOL portion or BEOL portion and a transistor configuration in the BEOL portion, and (iii) a wake-up/sleep circuit in the BEOL portion adapted for receiving an identifier. The wake-up/sleep circuit is operatively connected with the power gating switch and with the state recovery circuit. Responsive to receiving the identifier, the wake-up/sleep circuit causes the power gating switch to switch OFF/ON the supply power to the power isle and causes the state recovery circuit to store/restore the state of the power isle.

Abstract: An integrated circuit device comprising a power control unit for controlling the power of a power isle is disclosed. The power control unit comprises (i) a power gating switch implemented in the BEOL portion for switching ON/OFF the power to the power isle, (ii) a state recovery circuit comprising a memory element in the FEOL portion or BEOL portion and a transistor configuration in the BEOL portion, and (iii) a wake-up/sleep circuit in the BEOL portion adapted for receiving an identifier. The wake-up/sleep circuit is operatively connected with the power gating switch and with the state recovery circuit. Responsive to receiving the identifier, the wake-up/sleep circuit causes the power gating switch to switch OFF/ON the supply power to the power isle and causes the state recovery circuit to store/restore the state of the power isle.

Abstract: A Field-Programmable Gate Array device is provided with programmable interconnect points in the form of interconnect circuits comprising one or more pass transistors, wherein at least some components of the interconnect circuits are implemented in the Back-End-Of-Line part of the Field-Programmable Gate Array device's production process. The memory element in an interconnect point is not produced as a Static Random Access Memory cell, but as a Dynamic Random Access Memory cell, requiring only a single select transistor and a storage capacitor for each memory element. The fabrication of at least the select transistor and the pass transistor involves the use of a thin film semiconductor layer, e.g., Indium Gallium Zinc Oxide, enabling production of transistors with low leakage in the Back-End-Of-Line.