Abstract: Consistent with the present disclosure, multiple forward error correction (FEC) encoders are provided for encoding a respective one of a plurality of data streams. A mechanism is provided to mix or interleave portions of the encoded data such that each subcarrier carries information associated with each data stream, as opposed to each subcarrier carrying information associated with only a corresponding one of the data streams. As a result, both higher SNR and low SNR optical subcarriers carry such information, such that errors occurring during transmission are distributed and not concentrated or limited to information associated with a single data stream. Accordingly, at the receive end, each FEC decoder decodes information having a similar overall error rate. By balancing the error rates across each FEC encoder/decoder pair, the overall ability to correct errors improves compared to a system in which mixing or interleaving is not carried out.

Abstract: Consistent with the present disclosure, multiple forward error correction (FEC) encoders are provided for encoding a respective one of a plurality of data streams. A mechanism is provided to mix or interleave portions of the encoded data such that each subcarrier carries information associated with each data stream, as opposed to each subcarrier carrying information associated with only a corresponding one of the data streams. As a result, both higher SNR and low SNR optical subcarriers carry such information, such that errors occurring during transmission are distributed and not concentrated or limited to information associated with a single data stream. Accordingly, at the receive end, each FEC decoder decodes information having a similar overall error rate. By balancing the error rates across each FEC encoder/decoder pair, the overall ability to correct errors improves compared to a system in which mixing or interleaving is not carried out.

Abstract: Consistent with the present disclosure independent phase and frequency clock recovery on each SC. Both leaf and hub perform digital clock recovery on each SC by increasing the Rx-ADC sampling rate by a few ppm (˜16 ppm), and using a delay compensating element, together with gapped clocks. The gaps and delay compensating elements are independent on each SC. The delay element is performed using the frequency domain DSP engine, where the frequency domain equalizer coefficients are modified with a delay compensating element Thus, each SC can have its own fine timing frequency and timing phase tuning, and fine tracking of its own jitter. When the delay compensating element, which, for example, may include a finite impulse response (FIR) filter, reaches the end of its range, a clock gap equal to an integer number of symbols is performed. The delay element can be reset by the same number of symbols providing continuous phase interpolation.