Patents by Inventor Sofia Pediaditaki

Sofia Pediaditaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYNCHRONOUS MICROTHREADING
    Publication number: 20230315455
    Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
    Type: Application
    Filed: April 2, 2022
    Publication date: October 5, 2023
    Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
  • SYNCHRONOUS MICROTHREADING
    Publication number: 20230315445
    Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
    Type: Application
    Filed: April 2, 2022
    Publication date: October 5, 2023
    Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
  • SYNCHRONOUS MICROTHREADING
    Publication number: 20230315572
    Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
    Type: Application
    Filed: April 2, 2022
    Publication date: October 5, 2023
    Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
  • SYNCHRONOUS MICROTHREADING
    Publication number: 20230315460
    Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
    Type: Application
    Filed: April 2, 2022
    Publication date: October 5, 2023
    Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
  • SYNCHRONOUS MICROTHREADING
    Publication number: 20230315462
    Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
    Type: Application
    Filed: April 2, 2022
    Publication date: October 5, 2023
    Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
  • SYNCHRONOUS MICROTHREADING
    Publication number: 20230315461
    Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
    Type: Application
    Filed: April 2, 2022
    Publication date: October 5, 2023
    Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
  • SYNCHRONOUS MICROTHREADING
    Publication number: 20230315459
    Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
    Type: Application
    Filed: April 2, 2022
    Publication date: October 5, 2023
    Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
  • SYNCHRONOUS MICROTHREADING
    Publication number: 20230315444
    Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
    Type: Application
    Filed: April 2, 2022
    Publication date: October 5, 2023
    Inventors: David B. SHEFFIELD, Erich BOLEYN, Jonathan PEARCE, Sofia PEDIADITAKI, Jeffrey COOK, Shreesha SRINATH, Ching-Kai LIANG, Tyler SONDAG
  • APPARATUS AND METHOD FOR MANAGING UNSUPPORTED INSTRUCTION SET ARCHITECTURE (ISA) FEATURES IN A VIRTUALIZED ENVIRONMENT
    Publication number: 20220308867
    Abstract: An apparatus and method for supporting deprecated instructions.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: Tyler SONDAG, David SHEFFIELD, Sofia PEDIADITAKI
  • Inter-cluster communication of live-in register values
    Patent number: 10437590
    Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Sofia Pediaditaki, Ethan Schuchman, Rangeen Basu Roy Chowdhury, Manjunath Shevgoor
  • INTER-CLUSTER COMMUNICATION OF LIVE-IN REGISTER VALUES
    Publication number: 20190095203
    Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Sofia Pediaditaki, Ethan Schuchman, Rangeen Basu Roy Chowdhury, Manjunath Shevgoor