Abstract: The present disclosure introduces an apparatus for downhole measurement of a formation resistivity. The apparatus includes a probe having a button electrode, a first guard electrode insulated from the button electrode, a second guard electrode insulated from the first guard electrode, and a return electrode positioned external to the second guard electrode. The apparatus also includes an electrical source for setting a voltage drop between the second guard electrode and the return electrode, a first impedance (RBOG) electrically coupled between the button electrode and the second guard electrode, and a second impedance (RIGOG) electrically coupled between the first guard electrode and the second guard electrode.

Abstract: The present disclosure introduces an apparatus for downhole measurement of a formation resistivity. The apparatus includes a probe having a button electrode, a first guard electrode insulated from the button electrode, a second guard electrode insulated from the first guard electrode, and a return electrode positioned external to the second guard electrode. The apparatus also includes an electrical source for setting a voltage drop between the second guard electrode and the return electrode, a first impedance (RBOG) electrically coupled between the button electrode and the second guard electrode, and a second impedance (RIGOG) electrically coupled between the first guard electrode and the second guard electrode.

Abstract: An analysis circuit for analysing the RF response of an RF circuit, includes a voltage controlled oscillator (12), wherein a signal derived from voltage controlled oscillator output is applied as input to the RF circuit (10). A first mixer (18) mixes the RF circuit output with a first mixer signal derived from the voltage controlled oscillator and a second mixer (20) mixes the RF circuit unit output with a second mixer signal derived from the voltage controlled oscillator, the first and second mixer signals being 90 degrees out of phase. The mixer output signals are processed to provide the analysis. This analysis circuit uses mixers to enable baseband digital signal processing of signals to enable a frequency response characteristic of the RF circuit to be obtained. The analysis circuit essentially operates in the manner of an IF demodulator circuit.

Abstract: A wafer comprises i) at least one independent die having internal integrated components, a multiplicity of internal pads connected to some of the internal integrated components, ii) scribe lanes defined between and around each independent die, and in part of which are defined, for each die, at least a first group of external pads and/or a second group of external test integrated components. The external pads of each first group are connected, through conductive tracks, to a chosen one of the internal pads and/or internal integrated components of the associated die, and arranged to be fed with chosen test signals or to collect test result signals. Each external test integrated components of each second group is connected, through conductive tracks, to a chosen one of the die internal pads and/or die internal integrated components and/or to external pads of a first group.

Abstract: An analysis circuit for analysing the RF response of an RF circuit, comprises a voltage controlled oscillator (12), wherein a signal derived from voltage controlled oscillator output is applied as input to the RF circuit (10). A first mixer (18) mixes the RF circuit output with a first mixer signal derived from the voltage controlled oscillator and a second mixer (20) mixes the RF circuit unit output with a second mixer signal derived from the voltage controlled oscillator, the first and second mixer signals being 90 degrees out of phase. The mixer output signals are processed to provide the analysis. This analysis circuit uses mixers to enable baseband digital signal processing of signals to enable a frequency response characteristic of the RF circuit to be obtained. The analysis circuit essentially operates in the manner of an IF demodulator circuit.

Abstract: A wafer (W) comprises at least one die (D1-D6) comprising first (P1) and second (P2) complementary signal processing parts, scribe lanes (SL) defined between and around each die, and coupling means (CM) defined in at least a part of the scribe lanes (SL) and connecting i) the first part output of one of the dies (D1) to a second part input of at least one of the dies (D2) so that the first part output feeds the second part input with first output signals when it is fed with first input signals and configured to work, and so that the output of the fed second part (P2) delivers second output signals when it is configured to work, and/or ii) the second part output of one of the dies (D1) to a first part input of at least one of the dies (D2) so that the second part output feeds the first part input with second output signals when it is fed with second input signals and configured to work and so that the output of the fed first part (P1) delivers first output signals when it is configured to work.

Abstract: A wafer (W) comprises i) at least one independent die (D1, D2) having internal integrated components (IC), a multiplicity of internal pads (IP1-IP3) connected to some of the internal integrated components (IC), ii) scribe lanes (SL) defined between and around each independent die (Di), and in part of which are defined, for each die (D1, D2), at least a first group (G11, G12) of external pads (EP1-EP3) and/or a second group of external test integrated components (EC). The external pads (EP1-EP3) of each first group (G11, G12) are connected, through conductive tracks, to a chosen one of the internal pads (IP1-IP3) and/or internal integrated components (IC) of the associated die (D1, D2), and arranged to be fed with chosen test signals or to collect test result signals. Each external test integrated components of each second group is connected, through conductive tracks, to a chosen one of the die internal pads and/or die internal integrated components (IC) and/or to external pads of a first group.