Patents by Inventor Sofie MERTENS

Sofie MERTENS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240290368
    Abstract: The disclosed technology generally relates to a stack for a magnetic random access memory device, for example, a stack including a magnetic tunnel junction with a high tunneling magnetoresistance ratio. In one aspect, the stack includes a substrate layer, a first electrode layer arranged on the substrate layer, and seed metal layer arranged on the first electrode layer, each layer having a [001] or [010] or [100] in-plane texture. The stack further includes a magnetic free layer arranged on the seed metal layer, a crystalline tunnel barrier layer arranged on the free layer, a magnetic reference layer arranged on the crystalline tunnel barrier layer, a pinning layer arranged on the reference layer, and a second electrode layer arranged on the pinning layer.
    Type: Application
    Filed: February 26, 2024
    Publication date: August 29, 2024
    Inventors: Sofie Mertens, Kiroubanand Sankaran, Xiaoyu Piao, Robert Carpenter
  • Patent number: 10333059
    Abstract: The disclosed technology generally relates to forming a semiconductor structure and more particularly to forming a stack of layers of a semiconductor structure using a sacrificial layer that is removed during deposition of a functional layer. In one aspect, the disclosed technology relates to a method of protecting a top surface of a layer in a semiconductor structure. The method comprises: providing the layer on a substrate, the layer having an initial thickness and an initial composition; forming a sacrificial metal layer on and in contact with the layer, the sacrificial metal layer comprising a light metal element; and depositing by physical vapor deposition a functional metal layer on and in contact with the sacrificial metal layer. The sacrificial metal layer is removed by sputtering during the deposition of the functional metal layer, such that an interface is formed between the layer and the functional metal layer.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 25, 2019
    Assignee: IMEC vzw
    Inventors: Johan Swerts, Sofie Mertens
  • Publication number: 20160284987
    Abstract: The disclosed technology generally relates to forming a semiconductor structure and more particularly to forming a stack of layers of a semiconductor structure using a sacrificial layer that is removed during deposition of a functional layer. In one aspect, the disclosed technology relates to a method of protecting a top surface of a layer in a semiconductor structure. The method comprises: providing the layer on a substrate, the layer having an initial thickness and an initial composition; forming a sacrificial metal layer on and in contact with the layer, the sacrificial metal layer comprising a light metal element; and depositing by physical vapor deposition a functional metal layer on and in contact with the sacrificial metal layer. The sacrificial metal layer is removed by sputtering during the deposition of the functional metal layer, such that an interface is formed between the layer and the functional metal layer.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Johan SWERTS, Sofie MERTENS