Abstract: An apparatus includes a PWM ramp generator coupled between a switching node of a power converter and a first input of a comparator, the PWM ramp generator comprising a first resistor and a first capacitor connected in series between the switching node and the first input of the comparator, and a second resistor and a second capacitor connected in parallel between the first input of the comparator and a feedback node, and a PFM control circuit comprising an error amplifier and a current zero crossing detection comparator, wherein the error amplifier is coupled between a second input of the comparator and a reference node, and the PFM control circuit is configured to generate gate drive signal for the power converter when the power converter is configured to operate in a PFM mode.

Abstract: Voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator circuit comprises: a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch; an inductor coupled between the switching node and an output node; a capacitor coupled between the output node and ground; a driver configured to operate the first and second switches according to a pulse-width-modulated (PWM) signal; a PWM circuit configured to generate the PWM signal based on at least an error signal; and a phase detector configured to generate the error signal based on a phase difference between the PWM signal and a clock reference signal.

Abstract: Voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator circuit comprises: a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch; an inductor coupled between the switching node and an output node; a capacitor coupled between the output node and ground; a driver configured to operate the first and second switches according to a pulse-width-modulated (PWM) signal; a PWM circuit configured to generate the PWM signal based on at least an error signal; and a phase detector configured to generate the error signal based on a phase difference between the PWM signal and a clock reference signal.

Abstract: Voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator circuit comprises: a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch; an inductor coupled between the switching node and an output node; a capacitor coupled between the output node and ground; a driver configured to operate the first and second switches according to a pulse-width-modulated (PWM) signal; a PWM circuit configured to generate the PWM signal based on at least an error signal; and a phase detector configured to generate the error signal based on a phase difference between the PWM signal and a clock reference signal.

Abstract: Adaptive on-time switching voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator comprises: a switching circuit configured to generate a switching signal at a switching node according to a pulse-width modulated (PWM) signal; a phase-lock loop (PLL) configured to lock the PWM signal to a clock reference signal, the PLL comprising: a PWM signal generator configured to generate the PWM signal according to an error signal, and a phase detector configured to generate the error signal based on the PWM signal and the clock reference signal.

Abstract: Voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator circuit comprises: a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch; an inductor coupled between the switching node and an output node; a capacitor coupled between the output node and ground; a driver configured to operate the first and second switches according to a pulse-width-modulated (PWM) signal; a PWM circuit configured to generate the PWM signal based on at least an error signal; and a phase detector configured to generate the error signal based on a phase difference between the PWM signal and a clock reference signal.

Abstract: Adaptive on-time switching voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator comprises: a switching circuit configured to generate a switching signal at a switching node according to a pulse-width modulated (PWM) signal; a phase-lock loop (PLL) configured to lock the PWM signal to a clock reference signal, the PLL comprising: a PWM signal generator configured to generate the PWM signal according to an error signal, and a phase detector configured to generate the error signal based on the PWM signal and the clock reference signal.

Abstract: Voltage regulator circuits and methods therefor provided. In some embodiments, a voltage regulator circuit comprises: a first switch coupled to a power input; a second switch coupled to the first switch; a switching node between the first switch and the second switch; an inductor coupled between the switching node and an output node; a capacitor coupled between the output node and ground; a driver configured to operate the first and second switches according to a pulse-width-modulated (PWM) signal; a PWM circuit configured to generate the PWM signal based on at least an error signal; and a phase detector configured to generate the error signal based on a phase difference between the PWM signal and a clock reference signal.

Abstract: The present disclosure describes apparatuses and techniques of fast transient response for switching power regulators. In some aspects, an output voltage of a switching regulator operating in a discontinuous mode is monitored via a comparator coupled directly to an output of the switching regulator. In response to the output voltage falling below a predefined threshold, a high-side switch is activated to provide current to a load connected to the output of the switching regulator. The switching regulator is then transitioned from the discontinuous mode of operation to a continuous mode of operation to control subsequent operation of the high-side switch. This can be effective to mitigate a drop in the output voltage of the switching regulator when an amount of current consumed by the load increases (e.g., a load step).

Abstract: The present disclosure describes apparatuses and techniques of fast transient response for switching power regulators. In some aspects, a capacitor is disconnected from an output of a feedback amplifier of a switching power regulator that is operating in a discontinuous mode. This can be effective to prevent a voltage of the capacitor from discharging while the switching power regulator operates in the discontinuous mode. Responsive to the switching power regulator transitioning from the discontinuous mode to a continuous mode to provide an increased amount of current, the capacitor is connected to the output of the feedback amplifier. Connecting the non-discharged capacitor can be effective to enable the switching power regulator to provide the increased amount of current to the load more quickly.

Abstract: The present disclosure describes apparatuses and techniques of fast transient response for switching power regulators. In some aspects, a transconductance load is connected to a feedback amplifier of a switching power regulator that is operating in a discontinuous mode. This can be effective to dampen an indication, provided by the feedback amplifier, of voltage at an output of the switching power regulator while the regulator provides current to a load. Based on the dampened indication of the voltage, a current draw of the load is detected that exceeds the current provided to the load. Responsive to detecting the excessive current of the load, the switching regulator is transitioned to a continuous mode to provide an increased amount of the current to the load. Alternately or additionally, the increased amount of current can be allowed to exceed a nominal current limit protection threshold by a predefined amount of current, for a predefined number of switching cycles, or for a predefined amount of time.

Abstract: The present disclosure describes apparatuses and techniques of fast transient response for switching power regulators. In some aspects, a detection is made of a switching regulator's transition to a continuous mode of operation to provide current to a load. In response to the transition, a predefined current limit of the switching regulator's current-limit circuitry is increased effective to enable the switching regulator to draw an amount of input current that exceeds the predefined current limit. The switching regulator is then permitted to operate with the increased current limit for a predetermined number of cycles, which can be effective to enable the switching regulator to provide the current to the load more quickly.

Abstract: Aspects of the disclosure provide a circuit that includes a switch control circuit and a timing control circuit. The switch control circuit is configured to enable/disable a pulse width modulation (PWM) switch control to a regulator to transfer power to a load. The timing control circuit is configured to enable an analog to digital converter (ADC) to convert an analog signal to a digital stream when the PWM switch control is disabled in order to reduce noise in the digital stream due to switching activities in the regulator.

Abstract: A switching regulator includes a high-side driver configured to receive an input voltage, and a low-side driver configured to receive the input voltage. The high-side driver and the low-side driver are configured to provide an output voltage based on the input voltage. A charge pump module is configured to receive a supply voltage that varies between a first voltage level and a second voltage level greater than the first voltage level, generate the input voltage based on the supply voltage, and maintain the input voltage at the second voltage level independent of variations in the supply voltage.

Abstract: Systems and techniques for efficient power regulators with improved reliability. A power regulator may include a first driver including a first switch and a second switch, where a power dissipation of the first switch is less than a power dissipation of the second switch. The power regulator may include a second driver. The first and second switches may be implemented as transistors, which may have different on-state breakdown voltages and/or on-state drain source resistances.

Abstract: Systems and techniques for efficient power regulators with improved reliability. A power regulator may include a first driver including a first switch and a second switch, where a power dissipation of the first switch is less than a power dissipation of the second switch. The power regulator may include a second driver. The first and second switches may be implemented as transistors, which may have different on-state breakdown voltages and/or on-state drain source resistances.

Abstract: A method and system for providing a filter having an increased speed and decreased settling time are disclosed. The method and system comprise summing means for adding and subtracting. The method and system further comprise means coupled to the summer for providing a delay; and a clock coupled to the delay providing means. The clock determines a number of samples during a predetermined time. The clock is operated at a plurality of frequencies such that the total number of samples during the predetermined time is a predetermined number. According to the method and system disclosed, the filter has an increased speed. The increased speed of the filter can operate to extend the lifetime of power devices.

Abstract: A digital compensation circuit for calibrating a sensor includes a serial communication circuit for receiving data relating to a plurality of parameters and a plurality of registers coupled to the serial communication circuit; one of plurality of registers for reading temperature information. The digital compensation circuit further includes a digital trim circuit for adjusting the temperature information in the one of plurality of registers to a predetermined value at an initial calibration temperature. Finally, the digital compensation circuit further includes means responsive to the digital trim circuit for measuring gain and offset at a predetermined value of the physical parameter being measured.