Abstract: A method for manufacturing a FinFET having a fin that has a fin body includes selecting a desired electrical performance parameter, selecting a base dimension of the fin, identifying a combination of fin-body doping and fin-geometry that causes the FinFET to have the desired electrical performance parameter, doping the fin body according to the identified fin-body doping, and fabricating the fin according to the fin-geometry.

Abstract: A method for manufacturing a FinFET having a fm that has a fm body includes selecting a desired electrical performance parameter, selecting a base dimension of the fin, identifying a combination of fin-body doping and fin-geometry that causes the FinFET to have the desired electrical performance parameter, doping the fin body according to the identified fin-body doping, and fabricating the fm according to the fin-geometry.

Abstract: A semiconductor manufacture includes a first semiconductor including a substrate die having a first surface and having a second surface upon which integrated circuitry is disposed; a second semiconductor die; a through-silicon via (TSV) extending through the first semiconductor die and electrically connected to the second semiconductor die; and at least one ground plug including an electrically conductive material, positioned proximally to the TSV and extending into the substrate of the first semiconductor die from one of the first surface or the second surface.

Abstract: Hardware threading optimizes use of hardware resources in a dynamic workload environment. Unutilized hardware resources are dynamically borrowed to increase throughput performance and/or power savings by enabling parallel processing of application pipeline stages.

Abstract: A method, computer program product, and data processing system for automatically designing routing paths in an integrated circuit is disclosed. The present invention allows for the design of paths that are optimal in terms of the signal delay in circuits that may require registers for signal to travel over multiple clock cycles or in circuits that may contain multiple clock domains. An integrated circuit die is modeled as a weighted grid graph in which the edges represent wire segments and the weights represent the delays associated with those wire segments. Designing for optimum delay involves finding a shortest path between two vertices in the grid graph using a modified single-source shortest path algorithm. Registers, buffers, and dual-clock domain synchronizers are modeled according to a labeling function that assigns components to selected vertices in the routing path for optimal results.

Abstract: A method, computer program product, and data processing system for automatically designing routing paths in an integrated circuit is disclosed. The present invention allows for the design of paths that are optimal in terms of the signal delay in circuits that may require registers for signal to travel over multiple clock cycles or in circuits that may contain multiple clock domains.