Abstract: Apparatuses and methods for performing lookup operations are provided. A content addressable memory (CAM) module disposed on a first chip includes one or more content addressable memories. A random access memory (RAM) module disposed on the first chip is configured to receive a memory address from the CAM modules, the memory address being based on a search key received by the CAM module. The RAM module includes one or more random access memories configured to store data entries and counter values or timestamps for respective ones of the data entries. The RAM module also includes logic that is configured to compute the counter values or timestamps. The RAM module is configured to output a data entry corresponding to the search key, the data entry being stored in the one or more random access memories at the memory address, and a counter value or timestamp for the data entry.

Abstract: Apparatuses and methods for performing lookup operations are provided. A content addressable memory (CAM) module disposed on a first chip includes one or more content addressable memories. A random access memory (RAM) module disposed on the first chip is configured to receive a memory address from the CAM modules, the memory address being based on a search key received by the CAM module. The RAM module includes one or more random access memories configured to store data entries and counter values or timestamps for respective ones of the data entries. The RAM module also includes logic that is configured to compute the counter values or timestamps. The RAM module is configured to output a data entry corresponding to the search key, the data entry being stored in the one or more random access memories at the memory address, and a counter value or timestamp for the data entry.

Abstract: Apparatuses and methods for performing lookup operations are provided. A content addressable memory (CAM) module disposed on a first chip includes one or more content addressable memories. A random access memory (RAM) module disposed on the first chip is configured to receive a memory address from the CAM module, the memory address being based on a search key received by the CAM module. The RAM module includes one or more random access memories configured to store data entries and counter values or timestamps for respective ones of the data entries. The RAM module also includes logic that is configured to compute the counter values or timestamps. The RAM module is configured to output a data entry corresponding to the search key, the data entry being stored in the one or more random access memories at the memory address, and a counter value or timestamp for the data entry.

Abstract: Computer circuitry is provided for fast caching, which includes a memory, a processor, and a cache. The memory stores a data block. The processor retrieves the data block from the memory and determines whether to store the data block in the cache. The cache performs a first hash function on the data block in response to the processor determining to store the data block in the cache. The cache performs a second hash function on the data block if the first hash function results in a collision.

Abstract: Systems and techniques relating to processing of network communications include, according to an aspect, a network device that includes circuitry configured to receive value bits selected from a group consisting of a zero bit, a one bit, and a don't care bit; and circuitry configured to store encoded representations of the value bits for use in network packet routing, wherein the encoded representations are position bits selected from a group consisting of a zero bit and a one bit; wherein the circuitry configured to store includes a first memory location and a second memory location that each eliminate a different combination of the value bits from being available for storage respectively in the first memory location and the second memory location.

Abstract: Multi-port memory circuitry includes single-port memory circuitry, and arbitration logic circuitry that accepts multiple memory queries for the single-port memory circuitry and prevents the multiple memory queries from addressing conflicting portions of the single-port memory circuitry within a single clock cycle. The arbitration logic circuitry may include conflict-resolution logic circuitry that determines whether multiple memory queries address conflicting portions of the single-port memory circuitry. The single-port memory circuitry may be divided into a plurality of sub-arrays, and the conflict-resolution logic circuitry determines whether the multiple memory queries address overlapping groups of sub-arrays. The single-port memory circuitry may be a content-addressable memory or a random-access memory. The multi-port memory circuitry may be part of a shared-memory, multi-processor apparatus.

Abstract: The present disclosure describes systems and techniques relating to accessing data stored in Ternary Content Addressable Memory (TCAM). According to an aspect of the described systems and techniques, a device includes: several blocks of TCAM (Ternary Content Addressable Memory); a hash RAM (Random Access Memory); and processor electronics configured to pre-process control records to (i) identify a subset of bits of the control records, giving priority to bits with no X value, (ii) load the hash RAM based on the identified subset of the bits to be used for hashing of search records to find locations in the several blocks of TCAM, and (iii) order the control records in the several blocks of TCAM in accordance with the identified subset of the bits.

Abstract: The present disclosure describes systems and techniques relating to processing of network communications. According to an aspect of the described systems and techniques, a network device includes a content addressable memory (CAM) device including random access memory (RAM) devices; and a register configured to store a value for the RAM devices of the CAM device; wherein the CAM device is configured to retrieve data stored in the RAM devices of the CAM device, at a received address offset by the value stored in the register, for comparison to at least a portion of a search string received from a network processor to handle network packet processing.

Abstract: The present disclosure describes systems and techniques relating to calculation of array statistics. According to an aspect of the described systems and techniques, a device includes: a memory configured to store a data array and a counter array, wherein the data array includes multiple values, and each of the multiple values is encoded in a respective row of the data array, and wherein the counter array includes multiple counters, respective columns of the counter array correspond to respective ones of the counters, and rows of the counter array correspond with bit significance positions spanning the multiple counters; and processor electronics configured to add up a number bits found in respective columns of the data array using respective ones of the multiple counters.

Abstract: The present disclosure describes systems and techniques relating to processing of network communications. According to an aspect of the described systems and techniques, a network device includes a random access memory (RAM); a buffer coupled with the RAM; circuitry configured to copy data from a location in the RAM to the buffer responsive to a received identifier corresponding to a search key corresponding to a received packet; and circuitry configured to compare the data copied to the buffer with the search key to provide a result for use in forwarding of the packet, wherein don't care bits for the comparison are determined from a count of don't care bits encoded in a portion of the location in the RAM indicated by the identifier.

Abstract: The present disclosure describes systems and techniques relating to processing of network communications. According to an aspect of the described systems and techniques, a network device includes a content addressable memory (CAM); and processing circuitry configured to receive records to be stored in the CAM, compare the records to identify similar bit values at respective bit positions of at least a portion of the records, store in the CAM the similar bit values in a single sample record corresponding to the portion of the records, store in the CAM remaining non-similar bit values of the portion of the records, thereby compressing the portion of the records stored in the CAM, store in the CAM one or more remaining records of the received records not included in the portion of the records, and search the CAM including the compressed portion of the records and the one or more remaining records.

Abstract: Methods of booting a client data processing system attached to a control data processing system in a data processing network. At power-on or re-boot of a client system, an initial program load request is issued from the client system onto the network and responsive to the receipt of the initial program load request at the control system, bootstrap code is transferred to the client to cause the client to boot from operating system code stored on a mass storage device of the client; alternatively, bootstrap code is transferred to the client system to cause the client to boot from operating system stored on a mass storage device of the client, or bootstrap code is transferred to cause the client system to boot from the control system.

Abstract: An article for providing a visual deterrent against theft of a portable electronic device is provided. The portable electronic device such as a portable computer has a first portion, such as a keyboard and body part and a second portion such as a display hinged for rotation relative to the first portion. The article comprises a body arranged to prevent hinging of the second portion relative to the first portion and a lock for preventing removal of the body of the article from the portable electronic device.

Abstract: An error recovery technique is provided which is used during the automatic installation of software on a client data processing system from a connected server data processing system. The installation process is made up of a plurality of operations executing on the client, for example format client disk drive, load DOS, load Windows etc. Monitoring the successful completion of each of these operations on the client is watchdog timer code which preferably takes the form of device driver software received from the server system early in the installation process. At the beginning of each operation, a preselected time value is written to a counter in the watchdog timer, this time value representing a time period which is greater than the time normally taken for the operation to complete. If the counter expires before the operation is complete (if for example the server system or network fails), the client invokes an error recovery procedure which may for example involve rebooting the client.