Abstract: Embodiments disclosed herein include passive electrical components with thickness modifications in order to improve embedding processes. In an embodiment, such an apparatus comprises a substrate with a first width, where the substrate comprises a first surface, a second surface opposite from the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, a layer with a second width that is greater than the first width contacts the substrate and covers the sidewall surfaces and the first surface of the substrate.

Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

Abstract: Apparatus and methods for embedding deep trench capacitors (DTCs) in a package substrate. The method includes fabricating an integrated circuit on a silicon substrate core and identifying a deep trench capacitor (DTC) component to integrate with the integrated circuit. A cavity is created in the silicon substrate core to accommodate the DTC component. The cavity extends therethrough, like a through-hole. A temporary carrier is attached to the silicon substrate to create a cavity floor. A gap magnitude is determined, which is a difference between the thickness of the silicon substrate core and the thickness of the DTC component. An epoxy material with a minimum bond line that matches the gap magnitude is selected and implemented to fill the gap in fabrication. The minimum bond line is controlled by selection of particles to use in the epoxy material.

Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.

Abstract: Hybrid cores including adhesive promotion layers and related methods are disclosed. An example substrate core for an integrated circuit disclosed herein includes a frame including interior edge, a glass panel including an exterior edge, and an adhesion promotion layer disposed between the interior edge and the exterior edge.

Abstract: An integrated circuit package includes a substrate with an integrated circuit device mounting surface, and at least one optical fiber mount in the substrate. The optical fiber mount includes a support having at least one optical fiber mounting channel, and the optical fiber mounting channel is configured to mount at least one clad optical fiber.

Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a core made of glass and having a surface, the core further including a first region having a first concentration of ions and a second region having a second concentration of ions at the surface of the core; and a third region having a third concentration of ions, wherein the second region is between the third region and the surface of the core, and wherein the third concentration of ions is less than the first and second concentrations of ions; a dielectric with a conductive pathway at the surface of the core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.