Abstract: Architectures and methods for multi-layer filled through-glass vias (TGVs) in a glass core. The glass core includes a plurality of through-glass vias (TGVs), individual TGVs have a sidewall; a multi-layer fill material is within individual TGVs, wherein the multi-layer fill material is characterized by a layer of copper that is conformal to the sidewall, and at least one layer of a nickel and iron alloy within the layer of copper. The nickel and iron alloy can be Invar. The multi-layer fill material comprises materials and arrangements of materials to approximate a desired or target coefficient of thermal expansion (CTE) with respect to the glass core.

Abstract: Architectures and methods for through-glass vias (TGVs) filled with copper and negative thermal expansion (NTE) material in order to reduce the coefficient of thermal expansion (CTE) of the material in the TGVs. The NTE can be added to an electroplating solution. The desired or target CTE for the fill material in the TGV can be used to inform the selection of the specific NTE to use and the percentage of the NTE to use.

Abstract: According to the various aspects, a present tool assembly or apparatus includes a water delivery component configured to direct water to a workpiece, and a cutting component for removing material to form cut-streets for die singulation. The present tool assembly is configured to operate to remove build-up layers and other layers from a glass core of the workpiece in a wet environment and a dry environment, at cut-street locations, and perform methods for dicing the workpiece.

Abstract: Thin glass cores for integrated circuit (IC) packages. Recesses in a glass core may be selectively etched into a frontside and/or backside of the glass core to locally reduce the thickness of glass. A dielectric material may be applied over the glass to backfill the recesses. The glass may then be further thinned from a same side as the recess to reduce the thickness of regions outside of the recesses. Alternatively, the glass may then be further thinned from a side of the glass opposite the recess to reduce the thickness of regions outside of the recesses and also remove the lesser thickness of glass remaining at the location of the recess. Panels comprising the thin glass core may then be built-up with routing metallization and assembled with IC die.

Abstract: Architectures and process flows for frames for glass core hybrid panels for semiconductor packaging. The glass core includes a layer of glass defined by a planar area enclosed by one or more edges that are substantially orthogonal to the planar area and at least one through-glass via (TGV) in the layer of glass, substantially filled with a conductive material. The frame comprises a coefficient of thermal expansion (CTE) that can be manipulated based on selection of frame material and/or percentage of copper in the frame material. The frame has a CTE of less than 11. The frame can enclose a panel, sub-panel or wafer and can include one or more cavities therein for respective glass cores.

Abstract: An apparatus comprises a glass core comprising a top surface and a bottom surface opposite the top surface. A plurality of vias extending between the top and bottom surfaces. A metallization layer is over at least a portion of the top surface. An edge is between the top and bottom surfaces. The edge comprises one or more protrusions or one or more cavities. Each of the protrusions or cavities comprises a first surface parallel to the top surface, a second surface non-parallel to the top surface, and a polymer or a metal on the first or second surface.

Abstract: A microelectronic assembly includes a substrate with a first substrate face and a second substrate face opposite the first substrate face. An interposer is in the substrate. The interposer has a first interposer face facing the first substrate face and a second interposer face facing the second substrate face. A bridge die is over the interposer. The bridge die has a first bridge die face facing the second interposer face and a second bridge die face facing the second substrate face. A first set of electrical connections is between the first bridge die face and the second interposer face, and a second set of electrical connections is between the first interposer face and the substrate. The second set of electrical connections has a greater number of electrical connections than the first set of electrical connections.

Abstract: IC device package including an IC die embedded within a package substrate comprising two or more substrate cores. A cutout in a first substrate core exposes a surface of a second substrate core and an IC die is placed within the opening. A package metallization routing structure including conductive vias adjacent to the embedded IC die may be built up and terminate interconnect interfaces. One or more additional IC dies may be assembled with the package substrate, coupling the additional IC dies with the embedded IC die. In some examples, the embedded IC die comprises capacitors implementing a package-level voltage regulator.

Abstract: An apparatus includes a package substrate comprising a core having a first surface along a first plane and a second surface along a second plane, a semiconductor device disposed within an opening in the core, the semiconductor device having a third surface along a third plane and a fourth surface along a fourth plane, the third plane substantially parallel to the first plane, a first dielectric material disposed on the first surface of the core, the first dielectric material extends into the opening to fill a first gap between a wall of the opening and a lateral surface of the semiconductor device, and a second dielectric material disposed on the second surface of the core, the second dielectric material extends into the opening to fill a second gap between the second plane and the fourth plane.

Abstract: Embodiments disclosed herein include components that are embedded within a core of a package substrate. In an embodiment, such an apparatus may comprise a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, a cavity is provided through a thickness of the substrate, and a first layer is in the cavity. In an embodiment, the first layer has a first width. In an embodiment, a component is on the first layer, and the component has a second width that is smaller than the first width. In an embodiment, a second layer is provided between a sidewall of the cavity and a sidewall of the component.

Abstract: Embodiments disclosed herein include passive electrical components with thickness modifications in order to improve embedding processes. In an embodiment, such an apparatus comprises a substrate with a first width, where the substrate comprises a first surface, a second surface opposite from the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, a layer with a second width that is greater than the first width contacts the substrate and covers the sidewall surfaces and the first surface of the substrate.

Abstract: An apparatus includes a substrate core, which has a first height between a first surface and a second surface opposite the first surface. A die is within the substrate core. The die may include a deep trench capacitor. The die has a second height between a first side of the die and a second side opposite the first side. The first height is greater than the second height. A plurality of conductive vias extend from a plurality of conductive contacts at the first side of the die to the first surface of the substrate core. A material comprising a dielectric is disposed over the die and encapsulates the plurality of conductive vias. In some embodiments, a bond film is in contact with the second side of the die.

Abstract: An apparatus comprising a package substrate comprising a core layer; a pedestal embedded in the core layer; and a structure comprising a passive circuit component, wherein the structure is above the pedestal and is embedded in the core layer.

Abstract: Microelectronic integrated circuit package structures include one or more trench capacitors extending through a portion a device structure. The device structure is embedded within a portion of a core layer of a multi core package substrate, wherein one or more conductive interconnect structures are coupled with the one or more trench capacitors. A thickness of the device structure is equal to a thickness of the core layer.

Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

Abstract: Apparatus and methods for embedding deep trench capacitors (DTCs) in a package substrate. The method includes fabricating an integrated circuit on a silicon substrate core and identifying a deep trench capacitor (DTC) component to integrate with the integrated circuit. A cavity is created in the silicon substrate core to accommodate the DTC component. The cavity extends therethrough, like a through-hole. A temporary carrier is attached to the silicon substrate to create a cavity floor. A gap magnitude is determined, which is a difference between the thickness of the silicon substrate core and the thickness of the DTC component. An epoxy material with a minimum bond line that matches the gap magnitude is selected and implemented to fill the gap in fabrication. The minimum bond line is controlled by selection of particles to use in the epoxy material.

Abstract: Various techniques for alleviating crack formation and propagation in glass, and related devices and methods, are disclosed. The techniques are based on providing various edge features before singulation of a glass panel into individual glass units. In one aspect, an edge feature may be an opening in an edge region of a glass core, the opening extending from one of the faces of the glass core towards the opposite face of the glass core and comprising a fill material such as an insulator material, a polymer, or a conductive material. In another aspect, an edge feature may be an anchor comprising a first pad over one of the faces of a glass core, a second pad over the opposite face of the glass core, and a pin, wherein the pin is attached to the first pad and extends from the first pad into the glass core.

Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.

Abstract: Hybrid cores including adhesive promotion layers and related methods are disclosed. An example substrate core for an integrated circuit disclosed herein includes a frame including interior edge, a glass panel including an exterior edge, and an adhesion promotion layer disposed between the interior edge and the exterior edge.

Abstract: An integrated circuit package includes a substrate with an integrated circuit device mounting surface, and at least one optical fiber mount in the substrate. The optical fiber mount includes a support having at least one optical fiber mounting channel, and the optical fiber mounting channel is configured to mount at least one clad optical fiber.