Patents by Inventor Sohan Singh Mehta

Sohan Singh Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190079408
    Abstract: The disclosure is directed to a method for lithographic patterning. The method may include: exposing a photoresist to a radiant energy; developing the photoresist in a first developer, thereby creating an opening within the photoresist including sidewalls having a slant; and developing the photoresist in a second developer immediately after the developing of the photoresist in the first developer, thereby reducing the slant of the sidewalls of the opening. Where the photoresist is a positive tone development (PTD) photoresist, the first developer may include a positive developer, and the second developer may include a negative developer. Where the photoresist is a negative tone development (NTD) photoresist, the first developer may include a negative developer, and the second developer may include a positive developer.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Inventors: Sohan Singh Mehta, Mark C. Duggan, Sunil Kumar Singh, Robert Justin Morgan, SherJang Singh, Ravi Prakash Srivastava, Craig D. Higgins, Jason L. Behnke, Vineet Sharma
  • Patent number: 9691654
    Abstract: Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sunil Kumar Singh, Sohan Singh Mehta, Ravi Prakash Srivastava
  • Publication number: 20170178953
    Abstract: Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Sunil Kumar SINGH, Sohan Singh MEHTA, Ravi Prakash SRIVASTAVA
  • Patent number: 8350235
    Abstract: A system and method are provided for automatic dose-correction recipe generation, the system including a dose-correction recipe generator, a reticle data unit in signal communication with the recipe generator, a slit data unit in signal communication with the recipe generator, a process data unit in signal communication with the recipe generator, a wafer data unit in signal communication with the recipe generator, a control unit in signal communication with the recipe generator, and an output unit or a storage unit in signal communication with the control unit; and the method including receiving a current reticle data set and a previous reticle data set, receiving a current slit data set and a previous slit data set, receiving a process condition, receiving a wafer condition, automatically generating a dose-correction recipe in accordance with the received reticle, slit, process and wafer information, and controlling a dose in accordance with the generated recipe.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: January 8, 2013
    Assignees: Freescale Semiconductor, International Business Machines Corporation, Samsung Electronics Co., Ltd., Globalfoundries Singapore Pte., Ltd.
    Inventors: Hyung-Rae Lee, Dong Hee Yu, Sohan Singh Mehta, Niall Shepherd, Daniel A Corliss
  • Publication number: 20110017926
    Abstract: A system and method are provided for automatic dose-correction recipe generation, the system including a dose-correction recipe generator, a reticle data unit in signal communication with the recipe generator, a slit data unit in signal communication with the recipe generator, a process data unit in signal communication with the recipe generator, a wafer data unit in signal communication with the recipe generator, a control unit in signal communication with the recipe generator, and an output unit or a storage unit in signal communication with the control unit; and the method including receiving a current reticle data set and a previous reticle data set, receiving a current slit data set and a previous slit data set, receiving a process condition, receiving a wafer condition, automatically generating a dose-correction recipe in accordance with the received reticle, slit, process and wafer information, and controlling a dose in accordance with the generated recipe.
    Type: Application
    Filed: July 27, 2009
    Publication date: January 27, 2011
    Applicants: Chartered Semiconductor Manufacturing Ltd., Freescale Semiconductor, INTERNATIONAL BUSINESS MACHINES CORPORATION, Samsung Electronics Co., Ltd.
    Inventors: Hyung-Rae Lee, Dong Hee Yu, Sohan Singh Mehta, Niall Shepherd, Daniel A. Corliss