Abstract: An electronic apparatus included in an Internet of Things (IoT) network includes a communication interface, and at least one processor. The at least one processor is configured to, based on occurrence of an event in which control information allowing control over a target apparatus be provided, identify a target apparatus among at least one external apparatus connected with the electronic apparatus, broadcast a packet in association with providing the control information through the communication interface, receive identification information from an apparatus that responds to the packet through the communication interface, and based on the received identification information from the apparatus being included in a pre-stored contact list, provide the control information allowing control over the target apparatus to the apparatus.

Abstract: The inventive concept provides an integrated circuit device including: a substrate including a cell region and a peripheral circuit region; a plurality of bit line structures spaced apart from each other in the cell region with each bit line structure including a bit line conductive layer and a bit line capping layer on the bit line conductive layer; and a plurality of landing pads with each landing pad of the plurality of landing pads disposed on a respective bit line structure of the plurality of bit line structures and electrically connected to the substrate, wherein the peripheral circuit region includes a gate structure and a core capping layer on the gate structure; a direct contact plug extending vertically with respect to the substrate; first peripheral circuit wiring patterns extending laterally and spaced apart from each other on a first plane at a first vertical level relative to the substrate; and second peripheral circuit wiring patterns extending laterally and spaced apart from each other on a s

Abstract: A semiconductor device includes a substrate having an active region; a gate structure in the substrate, crossing the active region, and extending in a first horizontal direction; bit line structures crossing the gate structure and extending in a second horizontal direction, intersecting the first horizontal direction; a contact plug between the bit line structures; a landing pad structure on the contact plug and including a lower landing pad and an upper landing pad on the lower landing pad, wherein the lower landing pad includes a barrier layer and a metal layer on the barrier layer; and an insulating pattern on the lower landing pad and contacting a side surface of the upper landing pad. The upper landing pad is integrally coupled to the metal layer. A side surface of the insulating pattern includes a concave curved surface toward an adjacent bit line structure among the bit line structures.

Abstract: A method of fabricating a semiconductor device include providing a substrate including cell and peripheral regions, forming a cell gate structure on the cell region, forming a peripheral gate structure on the peripheral region, forming a bit-line structure on the cell region, forming a preliminary pad layer covering the bit-line structure and the peripheral gate structure, and etching the preliminary pad layer to form a landing pad and a peripheral conductive pad. The etching the preliminary pad layer includes forming a first mask structure on the preliminary pad layer, forming a second mask structure on the first mask structure, forming a first photoresist layer on the second mask structure, and using the first photoresist layer as an etching mask to etch the second mask structure. The first photoresist layer includes a first line opening overlapping the cell region, and peripheral resist patterns overlapping the peripheral region.

Abstract: A semiconductor memory device includes a substrate including a plurality of active regions in a memory cell region, a plurality of bit line structures extending in parallel with each other in a first horizontal direction in the memory cell region, a plurality of buried contacts respectively and electrically connected to the active regions and partially filling a space between the bit line structures, a plurality of lower landing pads in the space between the bit line structures and respectively on the buried contacts, a landing pad insulating structure in contact with the bit line structures and the lower landing pads and including a plurality of landing pad holes, a plurality of upper landing pads respectively filling the landing pad holes and respectively connected to the lower landing pads, and a plurality of capacitor structures.

Abstract: An integrated circuit device includes a bit line, an insulating capping pattern on the bit line and having an upper cutout portion, an insulating spacer on sidewalls of the bit line and the insulating capping pattern, a lower contact, a recess contact plug connected to the lower contact, an engraved insulating pattern on the insulating capping pattern and the recess contact plug and having a first portion, a second portion, and an opening, the first portion contacting a top surface of the insulating capping pattern, except for the upper cutout portion, the second portion being on a top surface of the recess contact plug, and the opening being defined by the first portion and the second portion, and a conductive landing pad in the opening of the engraved insulating pattern and having a lower corner portion contacting the upper cutout portion and a surface contacting the recess contact plug.

Abstract: A method of manufacturing an integrated circuit device includes forming, on a substrate, a plurality of bit line structures, which each include a bit line and an insulating capping pattern, and a plurality of contact plugs between the plurality of bit line structures, forming a plurality of recess contact plugs from the plurality of contact plugs and forming a plurality of recess spaces on the plurality of recess contact plugs, forming an engraved insulating pattern having openings, on the plurality of bit line structures and the plurality of recess contact plugs, forming a plurality of cut-off spaces by partially removing the insulating capping pattern of each bit line structure through the openings, and forming a plurality of conductive landing pads to respectively fill the plurality of recess spaces and the plurality of cut-off spaces and respectively contact upper surfaces of the plurality of recess contact plugs.

Abstract: An electroluminescent display including pixels arranged in a matrix is disclosed. Each pixel includes a pixel circuit configured to sample a threshold voltage of a driving element for driving a light emitting element and compensate for a data voltage. The pixel circuit includes a first switch element connected to a data voltage path supplied with the data voltage, a second switch element connected to a reference voltage path supplied with a predetermined reference voltage, a third switch element connected between a gate of the driving element and the first and second switch elements, a fourth switch element connected to an initialization voltage path supplied with a predetermined initialization voltage, and a fifth switch element connected to a power path supplied with a predetermined pixel driving voltage higher than the reference voltage and the initialization voltage.

Abstract: A display device may include: a display; an image input unit configured to obtain video content; a detector including at least one sensor; and a processor which may be configured to execute at least one instruction. The processor may be configured to, by executing the at least one instruction, detect a gesture of a user based on a result of detection by the at least one sensor while the video content is reproduced, and control the reproduction of the video content such that at least one frame corresponding to the detected gesture among a plurality of frames included in the video content is displayed on the display.

Abstract: A display apparatus includes a plurality of pixels each including an organic light emitting device and a pixel driving circuit. The pixel driving circuit includes a driving transistor controlling a driving current flowing in the organic light emitting device and a first, second, third, fourth, and fifth switching transistor, the third switching transistor selectively connecting a second node which is a drain electrode of the driving transistor to a third node which is a gate electrode of the driving transistor. The third switching transistor differs from a type of each of the driving transistor and the first, second, fourth, and fifth switching transistors. Accordingly, even when the organic light emitting display apparatus is driven at a low frequency, a bezel area is reduced, and a high resolution of a display panel is realized.

Abstract: A display device is provided in which each subpixel includes a driving TFT, an organic light-emitting diode, and at least one switching TFT for driving the subpixel. At least one of the driving TFT and the switching TFT is formed as a double-gate TFT having a first gate node and a second gate node, and each subpixel comprises a compensation circuit that senses a threshold voltage of the double-gate TFT and applies the same to the first gate node or the second gate node of the double-gate TFT.

Abstract: A display device is disclosed. The display device includes subpixels including data lines, scan lines, and one or more thin film transistors (TFTs). The display device includes a second switching TFT configured to output a reference signal input through a drain node to a source node according to a second scan signal input through a gate node, a first switching TFT configured to have a drain node connected to the source node of the second switching TFT, and form a current path such that the reference signal input through the drain node is transmitted to the data line according to a first scan signal input to a gate node, and an integrated circuit (IC) unit configured to sense a voltage of a current transmitted to the data line through the first switching TFT and sense a threshold voltage of the first switching TFT based on the sensed voltage.

Abstract: A display apparatus includes a plurality of pixels each including an organic light emitting device and a pixel driving circuit. The pixel driving circuit includes a driving transistor controlling a driving current flowing in the organic light emitting device and a first, second, third, fourth, and fifth switching transistor, the third switching transistor selectively connecting a second node which is a drain electrode of the driving transistor to a third node which is a gate electrode of the driving transistor. The third switching transistor differs from a type of each of the driving transistor and the first, second, fourth, and fifth switching transistors. Accordingly, even when the organic light emitting display apparatus is driven at a low frequency, a bezel area is reduced, and a high resolution of a display panel is realized.

Abstract: An electroluminescent display including pixels arranged in a matrix is disclosed. Each pixel includes a pixel circuit configured to sample a threshold voltage of a driving element for driving a light emitting element and compensate for a data voltage. The pixel circuit includes a first switch element connected to a data voltage path supplied with the data voltage, a second switch element connected to a reference voltage path supplied with a predetermined reference voltage, a third switch element connected between a gate of the driving element and the first and second switch elements, a fourth switch element connected to an initialization voltage path supplied with a predetermined initialization voltage, and a fifth switch element connected to a power path supplied with a predetermined pixel driving voltage higher than the reference voltage and the initialization voltage.

Abstract: A display device is disclosed. The display device includes subpixels including data lines, scan lines, and one or more thin film transistors (TFTs). The display device includes a second switching TFT configured to output a reference signal input through a drain node to a source node according to a second scan signal input through a gate node, a first switching TFT configured to have a drain node connected to the source node of the second switching TFT, and form a current path such that the reference signal input through the drain node is transmitted to the data line according to a first scan signal input to a gate node, and an integrated circuit (IC) unit configured to sense a voltage of a current transmitted to the data line through the first switching TFT and sense a threshold voltage of the first switching TFT based on the sensed voltage.

Abstract: A display device is provided in which each subpixel includes a driving TFT, an organic light-emitting diode, and at least one switching TFT for driving the subpixel. At least one of the driving TFT and the switching TFT is formed as a double-gate TFT having a first gate node and a second gate node, and each subpixel comprises a compensation circuit that senses a threshold voltage of the double-gate TFT and applies the same to the first gate node or the second gate node of the double-gate TFT.