Patents by Inventor Sohrab Safai
Sohrab Safai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9515034Abstract: A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.Type: GrantFiled: January 3, 2014Date of Patent: December 6, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Sohrab Safai, David B. Clegg, Tu-Anh N. Tran
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Patent number: 9111755Abstract: A semiconductor device comprises an integrated circuit including a wire bond pad and a passivation material, and a first gap between a first selected portion of the wire bond pad and the passivation material. The first gap is positioned to contain at least a first portion of a splash of the wire bond pad formed during a wire bond process.Type: GrantFiled: April 25, 2014Date of Patent: August 18, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Tu-Anh N. Tran, David B. Clegg, Sohrab Safai
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Publication number: 20150194396Abstract: A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.Type: ApplicationFiled: January 3, 2014Publication date: July 9, 2015Inventors: Sohrab SAFAI, David B. CLEGG, Tu-Anh N. TRAN
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Publication number: 20150194395Abstract: A method includes forming a conductive bond pad over a conductive structure in a last metal layer of an integrated circuit. A trench is etched around at least a portion of a perimeter of a wire bond region of the conductive bond pad. A portion of the conductive bond pad remains at the bottom of the trench to retain a conductive path between the wire bond pad region and the integrated circuit. The trench is positioned and sized to contain at least a portion of a splash of the conductive bond pad when a wire bond is subsequently formed in the wire bond region.Type: ApplicationFiled: January 3, 2014Publication date: July 9, 2015Inventors: Sohrab Safai, David B. Clegg, Tu-Anh N. Tran
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Patent number: 7015585Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.Type: GrantFiled: December 18, 2002Date of Patent: March 21, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Susan H. Downey, Sheila F. Chopin, Peter R. Harper, Sohrab Safai, Tu-Anh Tran, Alan H. Woosley
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Patent number: 6971929Abstract: A connector includes sheet metal contacts (40, 42) with termination ends (60, 62) for terminating to wires and with mating ends (70, 72) for mating to other contact devices such as circuit board pads. Each terminating end includes a wide groove part (90) with a groove bottom (94) that receives the wire insulation and with a pair of wide groove part wings (96, 98) that are crimped around the insulation. Each termination end also includes a narrow groove part (100) for receiving a bared conductor of the wire, the narrow groove part having a bottom (104) that is offset from the wide groove part bottom (94), and the narrow groove part having a pair of narrow groove part wings (106, 108) that are crimped around the wire conductor.Type: GrantFiled: March 31, 2004Date of Patent: December 6, 2005Assignee: ITT Manufacturing Enterprises, Inc.Inventors: Sohrab Safai, Carl Rodney Bunke, Chris Harold McDonald, Rene Augusto Mosquera
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Publication number: 20050221639Abstract: A connector includes sheet metal contacts (40, 42) with termination ends (60, 62) for terminating to wires and with mating ends (70, 72) for mating to other contact devices such as circuit board pads. Each terminating end includes a wide groove part (90) with a groove bottom (94) that receives the wire insulation and with a pair of wide groove part wings (96, 98) that are crimped around the insulation. Each termination end also includes a narrow groove part (100) for receiving a bared conductor of the wire, the narrow groove part having a bottom (104) that is offset from the wide groove part bottom (94), and the narrow groove part having a pair of narrow groove part wings (106, 108) that are crimped around the wire conductor.Type: ApplicationFiled: March 31, 2004Publication date: October 6, 2005Inventors: Sohrab Safai, Carl Bunke, Chris McDonald, Rene Mosquera
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Patent number: 6879028Abstract: A multi-die semiconductor package having an electrical interconnect frame. A top integrated circuit die is attached to the top side of an upper contact level of the frame and a bottom integrated circuit die is attached to the bottom side of the upper contact level of the frame. The die bond pads of the top die are electrically coupled (e.g. wired bonded) to pads of a lower contact level of the interconnect frame. The die bond pads of the bottom integrated circuit die are electrically coupled (e.g. wired bonded) to bond pads of the upper contact level of the frame. The bond pads of the lower contact level serve as external bond pads for the package. The frame may include inset structures, each having an upper portion located in the upper contact level and a lower portion located in the lower contact level.Type: GrantFiled: February 21, 2003Date of Patent: April 12, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Mark A. Gerber, Dae Y. Hong, Sohrab Safai
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Publication number: 20040164382Abstract: A multi-die semiconductor package having an electrical interconnect frame. A top integrated circuit die is attached to the top side of an upper contact level of the frame and a bottom integrated circuit die is attached to the bottom side of the upper contact level of the frame. The die bond pads of the top die are electrically coupled (e.g. wired bonded) to pads of a lower contact level of the interconnect frame. The die bond pads of the bottom integrated circuit die are electrically coupled (e.g. wired bonded) to bond pads of the upper contact level of the frame. The bond pads of the lower contact level serve as external bond pads for the package. The frame may include inset structures, each having an upper portion located in the upper contact level and a lower portion located in the lower contact level.Type: ApplicationFiled: February 21, 2003Publication date: August 26, 2004Inventors: Mark A. Gerber, Dae Y. Hong, Sohrab Safai
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Publication number: 20040119168Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.Type: ApplicationFiled: December 18, 2002Publication date: June 24, 2004Inventors: Susan H. Downey, Sheila F. Chopin, Peter R. Harper, Sohrab Safai, Tu-Anh Tran, Alan H. Woosley
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Patent number: 6508672Abstract: A filter connector (10) that includes a grounded shell (12) with an axis (14), a plurality of contacts (20) extending parallel to the axis, and a pi filter coupled to the contacts, the pi filter including a pair of planar capacitors (40, 42) with holes (50, 66) through which the contacts pass and ferrite beads (44) with holes through which the contacts pass. The invention provides connections between contact locations (104, 120) and conductive layers (80, 82) that extend around each hole of each planar capacitor. A coil spring (100) extends between a conductive layer on a rearward planar capacitor (42) and a shoulder (120) on a contact to establish an electrical connection there while biasing the contact rearwardly (R). A slideable retainer ring (112) is slid along the front end of the contact until it presses rearwardly against a conductive layer (80) on the front planar capacitor (40) and locks to the front portion of the contact at a location (104) that assures compression of the corresponding coil spring.Type: GrantFiled: December 19, 2001Date of Patent: January 21, 2003Assignee: ITT Manufacturing Enterprises, Inc.Inventor: Sohrab Safai
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Patent number: 6328615Abstract: A contact is formed of a terminus (12) that forms the rear termination end of the contact, and a mater (14) that forms the front contact mating end such as a socket (32) or pin, the front of the terminus being joined to the rear of the mater. The terminus front portion forms a groove (42, 138) and the mater rear end has a part (50, 154) that lies in the groove and is locked therein. The maters can be completely gold plated while the terminus is not plated at all, to minimize the use of gold while avoiding the need for masks to selectively plate only portions of a unitary contact. In one contact design, the groove (138) at the front end of the terminus opens forwardly (F) and is formed by concentric inner and outer groove walls (140, 142), with the rear end of the terminus having a cylindrical part (154) that fits into the groove with a press fit and/or crimp of the outer groove wall.Type: GrantFiled: March 2, 2000Date of Patent: December 11, 2001Assignee: ITT Manufacturing Enterprises, Inc.Inventor: Sohrab Safai
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Patent number: 6325669Abstract: A connector has a rigid insulator (32) with insulator passages (70), an elastomeric seal member (34) with seal passages (72) aligned with the insulator passages, and contacts (12, 14) with front ends lying in the rigid insulator passages and rear ends connected to wires (20, 22) that extend through and rearward of the seal member, which enables environmental sealing to the wires while permitting large contacts (12) to be installed through large seal member passages without damage to the seal member. A modular elastomeric insert (140) lies in each large seal passage, with its outside in interference fit with the seal passage (72) and its inside in interference fit with the wire (20), so the large diameter contact can be passed through the seal passage when the modular insert is not in place.Type: GrantFiled: July 6, 2000Date of Patent: December 4, 2001Assignee: ITT Manufacturing Enterprises, Inc.Inventor: Sohrab Safai
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Patent number: 5572066Abstract: A lead-on-chip (LOC) device (44) has a comb-shaped (32) or a cut-out (38) tape as the means of attachment for the leads (14) to the die surface. The LOC tape has cut-outs between the leads to minimize the amount of tape between the leads. The cut-outs are provided by either making the tape comb-shaped so that it has teeth and gaps between each tooth or by having oblong-shaped cut-outs in the tape corresponding in location the gaps between the leads. By minimizing the tape to die interface between the leads, the chance of voids forming between the leads is eliminated.Type: GrantFiled: January 3, 1995Date of Patent: November 5, 1996Assignee: Motorola Inc.Inventors: Sohrab Safai, Michael C. Przano
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Patent number: 4494305Abstract: A contact extraction tool in which a pair of spring arms may be squeezed together to force jaws on the ends of the arms inwardly through holes in the tip of the tool to firmly grip a contact therein while the tip is releasing contact retention element in a connector assembly to facilitate withdrawal of the contact from the assembly.Type: GrantFiled: November 26, 1982Date of Patent: January 22, 1985Assignee: International Telephone and Telegraph CorporationInventor: Sohrab Safai