Abstract: A method of fabricating a semiconductor device include providing a substrate including cell and peripheral regions, forming a cell gate structure on the cell region, forming a peripheral gate structure on the peripheral region, forming a bit-line structure on the cell region, forming a preliminary pad layer covering the bit-line structure and the peripheral gate structure, and etching the preliminary pad layer to form a landing pad and a peripheral conductive pad. The etching the preliminary pad layer includes forming a first mask structure on the preliminary pad layer, forming a second mask structure on the first mask structure, forming a first photoresist layer on the second mask structure, and using the first photoresist layer as an etching mask to etch the second mask structure. The first photoresist layer includes a first line opening overlapping the cell region, and peripheral resist patterns overlapping the peripheral region.

Abstract: A semiconductor memory device includes a substrate including a plurality of active regions in a memory cell region, a plurality of bit line structures extending in parallel with each other in a first horizontal direction in the memory cell region, a plurality of buried contacts respectively and electrically connected to the active regions and partially filling a space between the bit line structures, a plurality of lower landing pads in the space between the bit line structures and respectively on the buried contacts, a landing pad insulating structure in contact with the bit line structures and the lower landing pads and including a plurality of landing pad holes, a plurality of upper landing pads respectively filling the landing pad holes and respectively connected to the lower landing pads, and a plurality of capacitor structures.

Abstract: An integrated circuit device includes a bit line, an insulating capping pattern on the bit line and having an upper cutout portion, an insulating spacer on sidewalls of the bit line and the insulating capping pattern, a lower contact, a recess contact plug connected to the lower contact, an engraved insulating pattern on the insulating capping pattern and the recess contact plug and having a first portion, a second portion, and an opening, the first portion contacting a top surface of the insulating capping pattern, except for the upper cutout portion, the second portion being on a top surface of the recess contact plug, and the opening being defined by the first portion and the second portion, and a conductive landing pad in the opening of the engraved insulating pattern and having a lower corner portion contacting the upper cutout portion and a surface contacting the recess contact plug.

Abstract: A method of manufacturing an integrated circuit device includes forming, on a substrate, a plurality of bit line structures, which each include a bit line and an insulating capping pattern, and a plurality of contact plugs between the plurality of bit line structures, forming a plurality of recess contact plugs from the plurality of contact plugs and forming a plurality of recess spaces on the plurality of recess contact plugs, forming an engraved insulating pattern having openings, on the plurality of bit line structures and the plurality of recess contact plugs, forming a plurality of cut-off spaces by partially removing the insulating capping pattern of each bit line structure through the openings, and forming a plurality of conductive landing pads to respectively fill the plurality of recess spaces and the plurality of cut-off spaces and respectively contact upper surfaces of the plurality of recess contact plugs.

Abstract: A method of manufacturing a semiconductor device includes forming a lower structure including a plurality of transistors, forming a conductive layer on the lower structure, forming first preliminary pad mask patterns and wiring mask patterns on the conductive layer, forming pad mask patterns by patterning the first preliminary pad mask patterns while protecting the wiring mask patterns, and etching the conductive layer using the pad mask patterns and the wiring mask patterns as an etching mask to form pad patterns and wiring patterns.