Patents by Inventor So Hyun JUNG
So Hyun JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11963439Abstract: The present disclosure relates to an organic electroluminescent compound and an organic electroluminescent device comprising the same. By comprising the compound according to the present disclosure, it is possible to produce an organic electroluminescent device having improved driving voltage, power efficiency, and/or lifetime properties compared to the conventional organic electroluminescent devices.Type: GrantFiled: August 24, 2022Date of Patent: April 16, 2024Assignee: Rohm and Haas Electronic Materials Korea Ltd.Inventors: Eun-Joung Choi, Young-Kwang Kim, Su-Hyun Lee, So-Young Jung, YeJin Jeon, Hong-Se Oh, Dong-Hyung Lee, Jin-Man Kim, Hyun-Woo Kang, Mi-Ja Lee, Hee-Ryong Kang, Hyo-Nim Shin, Jeong-Hwan Jeon, Sang-Hee Cho
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Publication number: 20240122069Abstract: The present disclosure relates to a plurality of host materials and organic electroluminescent devices comprising the same. The present disclosure may provide a plurality of host materials having a composition favorable to thermal denaturation due to a low deposition temperature, while improving hole properties and electronic properties of HOMO and LUMO, by comprising separate compounds represented by formulas 1 and 2 into a light-emitting layer. By comprising the plurality of host materials of the present disclosure, it is possible to provide an organic electroluminescent device having a lower driving voltage, higher luminous efficiency and/or longer lifetime.Type: ApplicationFiled: November 10, 2023Publication date: April 11, 2024Inventors: Bitnari KIM, Su-Hyun LEE, So-Young JUNG, Hyo-Soon PARK, Tae-Jun HAN, Young-Jun CHO, Sang-Hee CHO
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Publication number: 20240114778Abstract: The present disclosure relates to an organic electroluminescent compound, a plurality of host materials, and an organic electroluminescent device comprising the same. By comprising the compound according to the present disclosure or by comprising a specific combination of compounds according to the present disclosure as a plurality of host materials, it is possible to produce an organic electroluminescent device having improved driving voltage, luminous efficiency, and/or lifetime properties compared to the conventional organic electroluminescent devices.Type: ApplicationFiled: August 14, 2023Publication date: April 4, 2024Inventors: So-Young JUNG, Hyo-Nim SHIN, Seung-Hyun YOON, Hyun-Ju KANG, Ye-Jin JEON, Tae-Jun HAN, Mi-Ja LEE, Dong-Gil KIM, Sang-Hee CHO
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Patent number: 11950506Abstract: The present disclosure relates to a plurality of host materials comprising a first host material comprising a compound represented by formula 1, and a second host material comprising a compound represented by formula 2, and an organic electroluminescent device comprising the same. By comprising a specific combination of compounds as host materials, it is possible to provide an organic electroluminescent device having lower driving voltage, higher luminous efficiency, higher power efficiency, and/or superior lifespan characteristics compared to conventional organic electroluminescent devices.Type: GrantFiled: October 20, 2020Date of Patent: April 2, 2024Assignee: Rohm and Haas Electronic Materials Korea Ltd.Inventors: So-Young Jung, Su-Hyun Lee, Mi-Ja Lee, Sang-Hee Cho, Doo-Hyeon Moon
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Patent number: 11557523Abstract: A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.Type: GrantFiled: February 5, 2021Date of Patent: January 17, 2023Assignee: SK hynix Inc.Inventors: Jae Woong Yu, So Hyun Jung
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Publication number: 20210159137Abstract: A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.Type: ApplicationFiled: February 5, 2021Publication date: May 27, 2021Applicant: SK hynix Inc.Inventors: Jae Woong YU, So Hyun JUNG
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Patent number: 10950512Abstract: A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.Type: GrantFiled: December 21, 2018Date of Patent: March 16, 2021Assignee: SK hynix Inc.Inventors: Jae Woong Yu, So Hyun Jung
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Patent number: 10879160Abstract: The semiconductor package includes a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines.Type: GrantFiled: December 14, 2018Date of Patent: December 29, 2020Assignee: SK hynix Inc.Inventors: Jae Woong Yu, So Hyun Jung
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Publication number: 20190237397Abstract: There is provided a method of forming a semiconductor package and a semiconductor package. The semiconductor package includes a package substrate. The package substrate includes a base layer, a first group of conductive lines disposed on a first surface of the base layer, and a second group of conductive lines disposed on a second surface of the base layer and electrically connected to respective ones of the first group of conductive lines. The package substrate further includes a plating lead line connected to one of the first group of conductive lines.Type: ApplicationFiled: December 14, 2018Publication date: August 1, 2019Applicant: SK hynix Inc.Inventors: Jae Woong YU, So Hyun JUNG
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Publication number: 20190237376Abstract: A package substrate of a semiconductor package includes conductive lines of a first layer disposed on a first surface of a base layer and conductive lines of a second layer disposed on a second surface of the base layer. An opening hole located between a first remaining portion and a second remaining portion to separate the first and second remaining portions from each other. The first remaining portion is electrically connected to a first conductive line among the conductive lines of the second layer, and the second remaining portion is electrically connected to a second conductive line among the conductive lines of the second layer.Type: ApplicationFiled: December 21, 2018Publication date: August 1, 2019Applicant: SK hynix Inc.Inventors: Jae Woong YU, So Hyun JUNG
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Patent number: 9536861Abstract: A semiconductor package may include a substrate having a first surface and a second surface facing away from the first surface, a window defined through a center portion of the substrate, and a plurality of first bond fingers, a plurality of second bond fingers, and a plurality of external electrodes arranged on the second surface; two or more first semiconductor chips each having a plurality of first bonding pads arranged adjacent to edges of the first semiconductor chips, and each of the first semiconductor chips separately attached to the first surface of the substrate in a face-down type position exposing the first bonding pads; and a second semiconductor chip having a plurality of second bonding pads arranged at a center portion of the second semiconductor chip, and attached to each of the first semiconductor chips in a face-down type position exposing the second bonding pads through the window.Type: GrantFiled: April 21, 2015Date of Patent: January 3, 2017Assignee: SK HYNIX INC.Inventors: Jae Woong Yu, Jong Seo Jung, So Hyun Jung, Seong Cheol Shin
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Publication number: 20160172331Abstract: A semiconductor package may include a substrate having a first surface and a second surface facing away from the first surface, a window defined through a center portion of the substrate, and a plurality of first bond fingers, a plurality of second bond fingers, and a plurality of external electrodes arranged on the second surface; two or more first semiconductor chips each having a plurality of first bonding pads arranged adjacent to edges of the first semiconductor chips, and each of the first semiconductor chips separately attached to the first surface of the substrate in a face-down type position exposing the first bonding pads; and a second semiconductor chip having a plurality of second bonding pads arranged at a center portion of the second semiconductor chip, and attached to each of the first semiconductor chips in a face-down type position exposing the second bonding pads through the window.Type: ApplicationFiled: April 21, 2015Publication date: June 16, 2016Inventors: Jae Woong YU, Jong Seo JUNG, So Hyun JUNG, Seong Cheol SHIN
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Patent number: 8907490Abstract: Semiconductor packages are provided. The semiconductor package includes a first chip having a first inclined sidewall in an edge of the first chip; and a second chip having a second inclined sidewall in an edge of the second chip and the second chip being horizontally adjacent to the first chip such that the first and second inclined sidewalls are in substantial contact with each other.Type: GrantFiled: September 14, 2012Date of Patent: December 9, 2014Assignee: SK Hynix Inc.Inventors: So Hyun Jung, Bok Gyu Min
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Publication number: 20130249108Abstract: Semiconductor packages are provided. The semiconductor package includes a first chip having a first inclined sidewall in an edge of the first chip; and a second chip having a second inclined sidewall in an edge of the second chip and the second chip being horizontally adjacent to the first chip such that the first and second inclined sidewalls are in substantial contact with each other.Type: ApplicationFiled: September 14, 2012Publication date: September 26, 2013Applicant: SK HYNIX INC.Inventors: So Hyun JUNG, Bok Gyu MIN