Abstract: Provided is a semiconductor device including a conductive contact plug on a substrate, the conductive contact plug including a lower portion and an upper portion on the lower portion, the lower portion having a first width, and the upper portion having a second width less than the first width, a bit line structure on the conductive contact plug, the bit line structure including a conductive structure and an insulation structure provided in a vertical direction perpendicular to an upper surface of the substrate, and a first lower spacer, a second lower spacer, and a third lower spacer sequentially provided on a sidewall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein an uppermost surface of the third lower spacer is higher than an upper surface of the first lower spacer and an upper surface of the second lower spacer.

Abstract: Provided is a method performed by a system for distribution storage of blockchain transaction data based on an erasure code. The method includes performing RS encoding on a predetermined number of blockchain transaction original data; and after the RS encoding is performed, applying LRC encoding technique to blockchain transaction original data (LRC-encoded original data), which needs to be accessed high speed, among the RS-encoded transaction original data to encode and store the LRC-encoded original data, and repairing the LRC-encoded original data through decoding.

Abstract: An authority authentication system includes an electronic device configured to generate a first unique asymmetric key pair, including a first public key and a first private key, a certificate authority server configured to generate a unique asymmetric key certificate and a unique certificate chain, and inject the unique certificate chain into the electronic device, at least one owner terminal device configured to request authority authentication from the electronic device based on at least one owner certificates and at least one owner key pair corresponding to the at least one owner terminal device, the at least one owner key pair including at least one public owner key and at least one private owner key, a communication network including a secure communication channel configured to transmit and receive the at least one owner certificate and the at least one public owner key.

Abstract: A semiconductor device may include a plurality of active patterns disposed on a substrate, a gate structure extending in a first direction, a bit line structure extending in a second direction, and a plurality of capacitors electrically connected to the plurality of active patterns, respectively, the plurality of active patterns having a shape extending in a third direction oblique to the first and second directions, the gate structure passing through centers of the plurality of active patterns, the bit line structure connected to first end portions of the plurality of active patterns, the plurality of capacitors connected to second end portions of the plurality of active patterns, respectively, the first end portion and the second end portion positioned at opposite sides with respect to the gate structure, and the first end portion and the second end portion having point-symmetrical shapes with respect to a center of the active pattern.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of contact plugs spaced apart from each other on the semiconductor substrate, a plurality of first landing pads spaced apart from each other on the plurality of contact plugs, a landing insulating layer surrounding upper sidewalls of the plurality of first landing pads and covering upper portions of the plurality of first landing pads, a stopper insulating layer disposed on the landing insulating layer, and a plurality of second landing pads spaced apart from each other on the plurality of first landing pads, passing through the stopper insulating layer, and buried in landing opening holes formed in the landing insulating layer, the plurality of second landing pads being electrically and respectively connected to the plurality of first landing pads.

Abstract: A semiconductor device includes a first active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction, a first word line between the first edge portion and the second edge portion and extending in a second direction intersecting the first direction, a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction, and a storage node contact on the second edge portion, where the first edge portion includes a first top surface and a second top surface, and the second top surface of the first edge portion is closer to the second edge portion than the first top surface of the first edge portion.

Abstract: Disclosed is a semiconductor device comprising an active pattern including first and second edge parts spaced apart from each other in a first direction, a word line extending along a second direction between the first and second edge parts, a bit line extending along a third direction on the first edge part, a storage node contact on the second edge part, a first active pad between the bit line and the first edge part, and a second active pad between the storage node contact and the second edge part. The first active pad extends in the third direction more than the first edge part. The second active pad extends in a direction opposite to the third direction more than the second edge part.

Abstract: A semiconductor device includes an active pattern on a substrate; a gate structure extending through an upper portion of the active pattern; a bit line structure on a central portion of the active pattern; a lower contact plug on each of opposite end portions of the active pattern; and an upper contact plug structure on the lower contact plug. The upper contact plug structure includes a first upper contact plug and a second upper contact plug on the first upper contact plug. The second upper contact plug contacts the first upper contact plug. The first upper contact plug includes a first metal pattern and a barrier pattern covering a lower surface and a sidewall of the first metal pattern. An upper surface of the bit line structure contacts a lower surface of the second upper contact plug and does not contact the barrier pattern.

Abstract: A computing device in a trusted computing (TC) system and an attestation method thereof are provided. The computing device includes at least one processor configured to operate as instructed by program code, the program code including: transmission code configured to cause the at least one processor to transmit, to a master controller, a first identification (ID) for a first device selected among a plurality of devices included in the TC system, a second ID for a second device selected among the plurality of devices, and a nonce; and attestation code configured to cause the at least one processor to perform attestation for the first device and the second device based on an aggregated signature, wherein the aggregated signature is based on generation of a first signature, by the first device, by using the nonce, and generation of a second signature, by the second device, by using the first signature.

Abstract: A semiconductor device includes an active pattern on a substrate; a bit line structure on a central portion of the active pattern; a first spacer structure and a second spacer structure disposed on a first sidewall and a second sidewall, respectively, of the bit line structure, the first sidewall and the second sidewall of the bit line structure facing each other in the first direction; a lower contact plug on each of opposite end portions of the active pattern; and an upper contact plug on the lower contact plug. The upper contact plug may include a conductive pattern; and a conductive spacer covering a lower surface of the conductive pattern, wherein the conductive spacer contacts an outer sidewall of the first spacer structure, and does not contact an outer sidewall of the second spacer structure.

Abstract: An integrated circuit device includes a substrate having an active area, a plurality of bit line structures on the substrate, the plurality of bit line structures including insulating spacers on sidewalls thereof, a buried contact between the plurality of bit line structures and electrically connected to the active area, an insulation capping pattern on a bit line structure of the plurality of bit line structures, and a landing pad electrically connected to the buried contact, the landing pad arranged to vertically overlap the bit line structure on the insulation capping pattern, wherein an uppermost surface of the landing pad is higher than an uppermost surface of the insulation capping pattern, relative to the substrate.

Abstract: A system for constructing a database for a structure and a property of a material based on big data includes an input module that receives chemical information about the material based on the big data, a controller that obtains information about the structure and the property of the material by modeling the chemical information about the material based on quantum mechanics and calculating elastic constants, a database constructing module that constructs a database for the information about the structure and the property, and an output module that outputs the information about the structure and the property in the database with respect to a model selected through the modeling.

Abstract: Provided is a method performed by a system for distribution storage of blockchain transaction data based on an erasure code. The method includes performing RS encoding on a predetermined number of blockchain transaction original data; and after the RS encoding is performed, applying LRC encoding technique to blockchain transaction original data (LRC-encoded original data), which needs to be accessed high speed, among the RS-encoded transaction original data to encode and store the LRC-encoded original data, and repairing the LRC-encoded original data through decoding.

Abstract: The present invention relates to a nanoscale thermoelectric assembly assembled through non-covalent contact between graphene and molecules, and a thermoelectric device comprising same. The present invention ascertains an increase in the Seebeck value due to n-type doping induced by an electron interaction in non-covalent contact of molecules, and confirms the length dependence of the Seebeck value in a graphene-alkylamine SAM system, thereby enabling the development and industrial application of efficient organic thermoelectric devices at a molecular scale.

Abstract: An electronic apparatus includes a memory configured to store instructions, and a processor configured to execute the instructions to receive a text of a first language, generate, based on the text of the first language, style information indicating a translation style to be applied to the text of the first language and machine-translate the text of the first language into text of a second language based on the generated style information.

Abstract: Disclosed are a method, a system, and a recording medium for expanding and utilizing data using pseudonym association. The method of expanding and utilizing data using pseudonym association includes receiving pseudonym association data in which first-party information of a customer company and third-party information of an entity other than the customer company are pseudonymized and combined; generating an interpretation model for data estimation by modeling the pseudonym association data; estimating the third-party information using target information of the customer company through the interpretation model; and providing the estimated third-party information for a service related to the customer company.

Abstract: A semiconductor device includes a substrate having an active region; a bit line structure on the substrate and extending in one direction; a bit line contact electrically connecting a first impurity region of the active region and the bit line structure; and a storage node contact disposed on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region, wherein the storage node contact includes a vertical extension portion extending in a vertical direction, perpendicular to an upper surface of the substrate, and a horizontal extension portion integrally connected to the vertical extension portion and extending in a horizontal direction, parallel to the upper surface of the substrate.

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

Abstract: A semiconductor device including a first contact plug structure on a substrate, a lower spacer structure on a sidewall of the first contact plug structure, and a bit line structure on the first contact plug structure and including a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate may be provided. The first contact plug structure may include a conductive pad contacting the upper surface of the substrate, an ohmic contact pattern on the conductive pad, and a conductive filling pattern on the ohmic contact pattern. The conductive filling pattern may include metal, and include a lower portion having a relatively large width and an upper portion having a relatively small width. The lower spacer structure may contact a sidewall of the conductive filling pattern.

Abstract: A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.