Abstract: A semiconductor device includes a substrate having an active region; a bit line structure on the substrate and extending in one direction; a bit line contact electrically connecting a first impurity region of the active region and the bit line structure; and a storage node contact disposed on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region, wherein the storage node contact includes a vertical extension portion extending in a vertical direction, perpendicular to an upper surface of the substrate, and a horizontal extension portion integrally connected to the vertical extension portion and extending in a horizontal direction, parallel to the upper surface of the substrate.

Abstract: Provided is a method of controlling driving of a vehicle using advance information, the method including acquiring preset local information including a road name, a road section, a road attribute, a location of a building, a lane, a traffic signal, and obstacle information for a predetermined region, acquiring a driving experience value resulting from a previous drive using the local information, and setting a target speed corresponding to the road attribute using the driving experience value, determining a driving state and a driving speed of the vehicle on the basis of the local information, and the target speed, of a current position of the vehicle, and generating a driving control command corresponding to the driving state and the driving speed.

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

Abstract: A semiconductor device including a first contact plug structure on a substrate, a lower spacer structure on a sidewall of the first contact plug structure, and a bit line structure on the first contact plug structure and including a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate may be provided. The first contact plug structure may include a conductive pad contacting the upper surface of the substrate, an ohmic contact pattern on the conductive pad, and a conductive filling pattern on the ohmic contact pattern. The conductive filling pattern may include metal, and include a lower portion having a relatively large width and an upper portion having a relatively small width. The lower spacer structure may contact a sidewall of the conductive filling pattern.

Abstract: A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

Abstract: A semiconductor memory device includes active patterns spaced apart from each other in first and second directions intersecting each other, each active pattern having a central portion, a first end portion, and a second end portion, bit line contacts disposed on the central portions and spaced apart from each other in the first and second directions, separation insulating patterns, each of which is disposed between the bit line contacts adjacent to each other in the first and second directions, intermediate insulating patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the first direction, and connection patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the second direction.

Abstract: Provided is an electronic apparatus that includes a microphone; a communication interface; a memory storing information on a first encoder, a first decoder, a first interpretation model comprising a first version conversion module, and at least one first version which the first conversion module may convert; and a processor. The processor is configured to communicate with an external device and receive information about at least one second version corresponding to a second interpretation model in the external device; obtain information on a compatible version based the at least one first version and the least one second version; based on a user voice, obtain a first feature vector corresponding to the user voice using the first encoder, convert the first feature vector to a second feature vector corresponding to the compatible version, and transmit the second feature vector to the external device.

Abstract: Provided is a semiconductor device including a conductive contact plug on a substrate, the conductive contact plug including a lower portion and an upper portion on the lower portion, the lower portion having a first width, and the upper portion having a second width less than the first width, a bit line structure on the conductive contact plug, the bit line structure including a conductive structure and an insulation structure provided in a vertical direction perpendicular to an upper surface of the substrate, and a first lower spacer, a second lower spacer, and a third lower spacer sequentially provided on a sidewall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein an uppermost surface of the third lower spacer is higher than an upper surface of the first lower spacer and an upper surface of the second lower spacer.

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

Abstract: A semiconductor device includes a substrate having an active area and a non-active area. An extra pad layer is disposed on the active area of the substrate. A first contact layer is disposed in a contact hole defined inside the substrate from a surface of the extra pad layer. A first silicide layer is disposed on both sidewalls of the first contact layer. A buried insulating layer is buried in the contact hole at lateral sides of the first contact layer and the first silicide layer. A second silicide layer is disposed on an upper surface and sidewalls of the extra pad layer. A second contact layer is on the buried insulating layer and the second silicide layer and is in direct contact with the second silicide layer.

Abstract: An electronic apparatus includes: a microphone; a communication interface including communication circuitry; a memory configured to store a first encoder corresponding to a first language and a first decoder corresponding to the first language; and a processor configured to: based on a user voice in the first language being received through the microphone, acquire text in the first language corresponding to the user voice, acquire a first feature vector by inputting the text in the first language to the first encoder, control the communication interface to transmit the first feature vector to an external device, and based on a second feature vector being received from the external device through the communication interface, acquire text in the first language corresponding to the second feature vector by inputting the second feature vector to the first decoder.

Abstract: A semiconductor memory device may include a substrate including active regions. Word lines may be on the active regions and may be extended in a first direction. Bit line structures may be on the word lines, and each of the bit line structures may include a contact portion, which is connected to a first impurity region of an active region, and a line portion, which is on the contact portion and which extends in a second direction. Contact plugs may be between the bit line structures and may be connected to respective second impurity regions of the active regions. Connection patterns may connect the contact plugs to the second impurity regions. Each of the connection patterns may include a first concave surface that faces the contact portion and a second convex surface that is opposite to the first surface.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

Abstract: A semiconductor device includes a one-time programmable (OTP) memory device, a key register and a key protection control logic. The OTP memory device stores a secret value, a key protection bit indicating whether to protect the secret value, and an end of life bit indicating whether to discard the semiconductor device. The key register loads the secret value from the OTP memory device and stores the secret value. The key protection control logic controls loading of the secret value from the OTP memory device to the key register based on the key protection bit and the end of life bit. Security of the secret value is enhanced and utilization of the secret value is optimized using the key protection bit and the end of life bit.

Abstract: A semiconductor device includes a semiconductor substrate provided with active regions, an isolation layer defining each active region on the semiconductor substrate, gate electrodes overlapping the active regions and extending in a first direction parallel to an upper surface of the semiconductor substrate, an insulating barrier structure disposed at a level higher than a level of where the gate electrodes are disposed, the insulating barrier structure having a grid pattern including grid cells, bitlines extending in a second direction perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate, and disposed at a level higher than a level of where the insulating barrier structure is disposed, and first contact plugs, each first contact plug being disposed in a corresponding grid cell of the grid cells of the insulating barrier structure.

Abstract: A semiconductor device includes a conductive contact plug disposed on a substrate, a bit line structure disposed on the conductive contact plug, first and second spacers, and a capping pattern disposed on the first and second spacers. The conductive contact plug includes a lower portion that has a first width and an upper portion that has a second width narrower than the first width. The bit line structure includes a conductive structure and an insulation structure stacked in a vertical direction. The first and second spacers are stacked on a sidewall of the lower portion of the conductive contact plug in a horizontal direction. The capping pattern covers a sidewall of the upper portion of the conductive contact plug. The first spacer directly contacts the sidewall of the lower portion of the conductive contact plug and includes air.

Abstract: Provided is a semiconductor device including a substrate including a cell array area and a peripheral circuit area and including a plurality of first active areas defined in the cell array area and at least one second active area defined in the peripheral circuit area; a plurality of bit lines arranged in the cell array area of the substrate and extending in a first direction; a plurality of cell pad structures arranged between the bit lines and each including a first conductive layer, a first intermediate layer, and a first metal layer that are sequentially arranged on a top surface of the first active area; and a peripheral circuit gate electrode disposed on the peripheral circuit area of the substrate and including a second conductive layer, a second intermediate layer, and a second metal layer sequentially arranged on the at least one second active area.

Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

Abstract: The present invention relates to a thermoelectric measurement system based on a liquid eutectic gallium-indium electrode, whereby thermoelectric performance can be measured with excellent efficiency and high reproducibility even without construction of expensive equipment, various organic molecules as well as large-area molecular layers can be measured, and various thermoelectric materials, such as inorganic materials and inorganic-organic composite materials, can be measured. In addition, non-toxic liquid metal EGaIn is used as an upper electrode, so the damage to even a substance of measurement in the form of a nano-level thin film can be minimized, and the measurement of thermoelectric performance can be performed on even nano- to micro-level organic thermoelectric elements. Therefore, the thermoelectric measurement system is widely utilized across the thermoelectric element industry.