Patents by Inventor Soichi Isono
Soichi Isono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080189590Abstract: A magnetic disk controller includes an error check code generating unit that generates error check codes associated with the encoded pieces of writing data; a first buffer that stores a first encoded piece of writing data and a first error check code associated with the first encoded piece; a second buffer that stores a second encoded piece of writing data and a second error check code associated with the second encoded piece; and a buffer control unit that, in a first period, substantially concurrently with a writing of the first encoded piece and the first error check code from the first buffer into a first sector of the magnetic disk, stores the second encoded piece and the second error check code into the second buffer.Type: ApplicationFiled: February 1, 2008Publication date: August 7, 2008Applicant: MARVELL TECHNOLOGY JAPAN Y.K.Inventors: Soichi Isono, Minoru Tsukada, Tomoki Oura, Koji Takahashi
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Publication number: 20080189451Abstract: Among other disclosed subject matter, a magnetic disk controller includes an interface that receives and transmits data to be written into a magnetic disk. The magnetic disk controller includes a first buffer and a second buffer each of which temporarily stores data that is to be written into at least one sector of the magnetic disk. The magnetic disk controller includes an encoding unit that encodes the data stored in any of the first buffer and the second buffer into data representing a signal to be applied to the magnetic disk. A data width M between the encoding unit and the first and second buffers is at least equal to twice a data width N between the interface and the first and second buffers.Type: ApplicationFiled: February 1, 2008Publication date: August 7, 2008Applicant: Marvell Semiconductor, Inc.Inventors: Soichi Isono, Minoru Tsukada, Tomoki Oura, Koji Takahashi
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Publication number: 20070217050Abstract: Embodiments of the present invention provide a magnetic disk drive capable of controlling write/read positions by a method that takes the disturbance in the circumferential direction of a magnetic disk into consideration, thereby making it possible to improve the positioning accuracy. A magnetic disk drive in accordance with an embodiment of the present invention comprises: a magnetic recording medium on which information is written to each track thereof, the recording medium having a servo signal formed in the each track at specified intervals; a magnetic head including a read head for reading a signal from the magnetic recording medium, and a write head for writing information to the magnetic recording medium. At the time of writing/reading information by the magnetic head, a servo signal is detected from among signals read out by the read head.Type: ApplicationFiled: December 21, 2006Publication date: September 20, 2007Applicant: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Minoru Tsukada, Soichi Isono, Tomoki Oura, Yoshikatsu Fujii, Koji Takahashi
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Publication number: 20060248245Abstract: A storage system to be connected to a large-scale computer includes a plurality of host adaptors connected to a host device, a plurality of storage device for storing data from the host device, a plurality of disk adaptors connected to the storage devices, a plurality of caches for temporarily storing data transferred between the host adaptors and the disk adaptors, and two buses connected to the host disk adaptors, and the caches. The buses transfer data among the host and disk adaptors and the caches.Type: ApplicationFiled: June 29, 2006Publication date: November 2, 2006Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
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Patent number: 7120738Abstract: A storage system to be connected to a large-scale computer includes a plurality of host adaptors connected to a host device, a plurality of storage device for storing data from the host device, a plurality of disk adaptors connected to the storage devices, a plurality of caches for temporarily storing data transferred between the host adaptors and the disk adaptors, and two buses connected to the host disk adaptors, and the caches. The buses transfer data among the host and disk adaptors and the caches.Type: GrantFiled: August 22, 2001Date of Patent: October 10, 2006Assignee: Hitachi, Ltd.Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
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Publication number: 20050286152Abstract: Embodiments of the invention eliminate the unnecessary disk format margin to raise the format efficiency. In one embodiment, a disk control unit (MPU) predicts the variation of the next servo sector pulse interval based on each learnt servo sector pulse interval. From this predicted interval, an optimal variation of the data sector pulse interval is determined for the current servo sector pulse. This optimal variation is set to an internal register of the hard disk controller (HDC). Based on this set variation, an internal calculation circuit calculates a corrected data sector pulse interval. Thus, data sector pulses are output at intervals optimized on an individual servo sector basis.Type: ApplicationFiled: June 29, 2005Publication date: December 29, 2005Applicant: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Yoshikatsu Fujii, Soichi Isono, Tomoki Ooura, Minoru Tsukada
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Patent number: 6954876Abstract: Defect management information of a disk apparatus is read efficiently. Pieces of defective track information, which each indicate existence of defective tracks for a group of a plurality of tracks, are stored being associated with physical track numbers. And, pieces of defect information on defective tracks are stored in predetermined groups. Further, pieces of pointer information that indicate start addresses of storage address for the above-mentioned predetermined groups are stored. When a processing means receives an instruction of read or write to a track of a storage medium, the processing means refers to a piece of defective track information based on the above-mentioned addresses. When existence of a defective track is indicated, the processing means refers to a piece of pointer information corresponding to the group relating to the referred piece of defective track information.Type: GrantFiled: December 10, 2001Date of Patent: October 11, 2005Assignee: Hitachi Global Storage Technologies Japan, Ltd.Inventors: Hitoshi Ogawa, Takushi Nishiya, Soichi Isono, Tomoki Oura
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Patent number: 6581128Abstract: A storage system to be connected to a large-scale computer includes a plurality of host adaptors connected to a host device, a plurality of storage device for storing data from the host device, a plurality of disk adaptors connected to the storage devices, a plurality of caches for temporarily storing data transferred between the host adaptors and the disk adaptors, and two buses connected to the host disk adaptors, and the caches. The buses transfer data among the host and disk adaptors and the caches.Type: GrantFiled: August 22, 2001Date of Patent: June 17, 2003Assignee: Hitachi, Ltd.Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
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Patent number: 6578100Abstract: A storage system to be connected to a large-scale computer includes a plurality of first logical units connected to a host device, a plurality of second logical units connected to a storage device, a plurality of cache memories, and a common bus wired between these logical units and memories. The plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are all made in the form of modules. The modules are detachably mounted to the common bus disposed on a back plane. The storage device can be made up of a plurality of small-size storage units arranged in an array. Thus, the storage system realizes its scalability. Since the plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are duplexed and the common bus is made in the form of 2 channels, the storage system can perform degrade operation.Type: GrantFiled: November 15, 1999Date of Patent: June 10, 2003Assignee: Hitachi, Ltd.Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
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Patent number: 6493297Abstract: Multibeam optical disk record and reproduction apparatus and method, in which at least two light beams generated are concentrated in different positions of on recording tracks of a recording medium to record or reproduce data to or from the recording medium on the different positions at the same time. The light beams are moved independently of each other across the recording tracks so that any one light beam is movable during the recording or reproducing of data by another light beam. This allows parallel recording/reproducing with a plurality of light beams without producing areas unaccessed due to the jumps of the light beams.Type: GrantFiled: May 4, 1993Date of Patent: December 10, 2002Assignee: Hitachi, Ltd.Inventors: Soichi Isono, Satoshi Kawamura, Kiyoshi Honda, Toshimitsu Kaku, Hitoshi Komatsu, Yuji Yamane, Yasushi Fukuda, Toshio Niihara, Hiroshi Ide
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Publication number: 20020071193Abstract: Defect management information of a disk apparatus is read efficiently. Pieces of defective track information, which each indicate existence of defective tracks for a group of a plurality of tracks, are stored being associated with physical track numbers. And, pieces of defect information on defective tracks are stored in predetermined groups. Further, pieces of pointer information that indicate start addresses of storage address for the above-mentioned predetermined groups are stored. When a processing means receives an instruction of read or write to a track of a storage medium, the processing means refers to a piece of defective track information based on the above-mentioned addresses. When existence of a defective track is indicated, the processing means refers to a piece of pointer information corresponding to the group relating to the referred piece of defective track information.Type: ApplicationFiled: December 10, 2001Publication date: June 13, 2002Inventors: Hitoshi Ogawa, Takushi Nishiya, Soichi Isono, Tomoki Oura
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Publication number: 20010056527Abstract: A storage system to be connected to a large-scale computer includes a plurality of host adaptors connected to a host device, a plurality of storage device for storing data from the host device, a plurality of disk adaptors connected to the storage devices, a plurality of caches for temporarily storing data transferred between the host adaptors and the disk adaptors, and two buses connected to the host disk adaptors, and the caches. The buses transfer data among the host and disk adaptors and the caches.Type: ApplicationFiled: August 22, 2001Publication date: December 27, 2001Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
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Publication number: 20010054136Abstract: A storage system to be connected to a large-scale computer includes a plurality of host adaptors connected to a host device, a plurality of storage device for storing data from the host device, a plurality of disk adaptors connected to the storage devices, a plurality of caches for temporarily storing data transferred between the host adaptors and the disk adaptors, and two buses connected to the host disk adaptors, and the caches. The buses transfer data among the host and disk adaptors and the caches.Type: ApplicationFiled: August 22, 2001Publication date: December 20, 2001Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
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Patent number: 6282688Abstract: A recording apparatus includes a plurality of ECC units operating selectively and independently. A medium access unit reads data from a recording medium in a read mode, and writes data from a host device to the recording medium in a write mode. The data read out from the recording medium contains a reproduction data and a medium reproduction check symbol added to the reproduction data, and data written contains a recording data and a medium recording check symbol added to the recording data. The reproduction data or the recording data is stored in a buffer. In a read mode, the reproduction data from the medium access unit is transferred to the host device through the buffer and in the write mode, the recording data from the host device is transferred to the medium access unit through the buffer.Type: GrantFiled: March 27, 1997Date of Patent: August 28, 2001Assignee: Hitachi, Ltd.Inventors: Motoyasu Tsunoda, Syoichi Miyazawa, Soichi Isono, Akira Kojima, Noriyuki Karasawa, Fukashi Ohi, Takashi Oeda
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Patent number: 6094728Abstract: A disk array controller or a disk array system includes a disk array control unit having an MPU 8 and a user data transfer control unit having host interfaces 3 and 4 with a host computer 17, a memory 5 for temporarily storing data, a redundant data generator 7 for generating redundant data, multi-channel disk device interfaces 16a.about.16e and 12a.about.12e and a data transfer control circuit (DMAC) 6 for controlling the data transfer between the host interface, the memory, the redundant data generator and the disk device interface. Internal buses are of at least three-bus structure including a control bus (for MPU) 15, a host data bus 13 and a drive data bus 14.Type: GrantFiled: May 5, 1997Date of Patent: July 25, 2000Assignee: Hitachi, Ltd.Inventors: Masatoshi Ichikawa, Soichi Isono, Kiyoshi Honda, Jun Matsumoto
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Patent number: 6012119Abstract: A storage system to be connected to a large-scale computer includes a plurality of first logical units connected to a host device, a plurality of second logical units connected to a storage device, a plurality of cache memories, and a common bus wired between these logical units and memories. The plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are all made in the form of modules. The modules are detachably mounted to the common bus disposed on a back plane. The storage device can be made up of a plurality of small-size storage units arranged in an array. Thus, the storage system realizes its scalability. Since the plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are duplexed and the common bus is made in the form of 2 channels, the storage system can perform degrade operation.Type: GrantFiled: January 26, 1998Date of Patent: January 4, 2000Assignee: Hitachi, Ltd.Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono
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Patent number: 5892918Abstract: A parallel computer system and a block transfer method and computer program for use with the parallel computer system which includes at least one processing unit divided into a plurality of logical processing units and a connecting device which exchanges commands and acknowledgements with the processing unit. The connecting device edits into a single command or acknowledgement individual commands or acknowledgements to be sent to the logical processing units and sends the single command or acknowledgement to the processing unit. The single command or acknowledgement includes a header, a command or acknowledgement code, logical processing unit numbers and pieces of command or acknowledge information corresponding to the logical processing units. The processing unit divides the single command or acknowledge into the individual commands or acknowledgements for the logical processing units and notifies the latter of these commands or acknowledgements.Type: GrantFiled: March 11, 1997Date of Patent: April 6, 1999Assignee: Hitachi, Ltd.Inventors: Soichi Isono, Yuzuru Maya, Akira Ohtsuji
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Patent number: 5875460Abstract: A disk drive has two channels of upper interfaces, and one channel is connected to a disk array controller, and the other channel is connected between a plurality of disk drives. A data disk drive reads the old data on the recording medium, calculates the exclusive OR of the old data and the corresponding data from the disk array controller, and transfers it to a parity disk as pseudo-parity data from the other channel. The parity disk drive reads the old parity data on the recording medium, calculates the exclusive OR of the old parity data and the pseudo-parity data, and writes it as new parity data.Type: GrantFiled: November 21, 1997Date of Patent: February 23, 1999Assignee: Hitachi, Ltd.Inventors: Akira Kojima, Akihito Ogino, Soichi Isono
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Patent number: 5845328Abstract: A command is issued from a processing unit to an on-line storage unit and transferred from the on-line storage unit to a back-up storage unit. The received commands are processed in the respective storage units. An overhead of the on-line storage unit is reduced in a hot stand-by system. Storage contents of the on-line storage unit and the back-up storage unit are made coincident in a structure having a plurality of processing units, where the on-line storage unit and the back-up storage unit are connected through a channel device.Type: GrantFiled: December 12, 1996Date of Patent: December 1, 1998Assignee: Hitachi, Ltd.Inventors: Yuzuru Maya, Soichi Isono, Akira Ohtsuji
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Patent number: 5819054Abstract: A storage system to be connected to a large-scale computer includes a plurality of first logical units connected to a host device, a plurality of second logical units connected to a storage device, a plurality of cache memories, and a common bus wired between these logical units and memories. The plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are all made in the form of modules. The modules are detachably mounted to the common bus disposed on a back plane. The storage device can be made up of a plurality of small-size storage units arranged in an array. Thus, the storage system realizes its scalability. Since the plurality of first logical units, the plurality of second logical units, and the plurality of cache memories are duplexed and the common bus is made in the form of 2 channels, the storage system can perform degrade operation.Type: GrantFiled: March 17, 1997Date of Patent: October 6, 1998Assignee: Hitachi, Ltd.Inventors: Tatuya Ninomiya, Hidefumi Masuzaki, Hiroyuki Kurosawa, Naoya Takahashi, Yasuo Inoue, Hidehiko Iwasaki, Masayuki Hoshino, Soichi Isono