Patents by Inventor Soichi Shida

Soichi Shida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8809778
    Abstract: A pattern inspection apparatus configured to perform pattern inspection based on a SEM image previously measures distortion amount data representing a magnitude distribution of positional displacement caused by distortion of the SEM image in a scanning direction. When the pattern inspection is performed, the apparatus makes design data and the SEM image correspond to each other by adjusting at least one of the design data and the SEM image on the basis of the distortion amount data, and places a measurement region on the SEM image on the basis of a correspondence between the design data and the SEM image. The apparatus may further find a matching rate between a pattern of the design data and a pattern of the SEM image.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 19, 2014
    Assignee: Advantest Corp.
    Inventors: Ryuichi Ogino, Soichi Shida, Yoshiaki Ogiso
  • Publication number: 20130234020
    Abstract: A pattern inspection apparatus configured to perform pattern inspection based on a SEM image previously measures distortion amount data representing a magnitude distribution of positional displacement caused by distortion of the SEM image in a scanning direction. When the pattern inspection is performed, the apparatus makes design data and the SEM image correspond to each other by adjusting at least one of the design data and the SEM image on the basis of the distortion amount data, and places a measurement region on the SEM image on the basis of a correspondence between the design data and the SEM image. The apparatus may further find a matching rate between a pattern of the design data and a pattern of the SEM image.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 12, 2013
    Inventors: Ryuichi Ogino, Soichi Shida, Yoshiaki Ogiso
  • Patent number: 7791022
    Abstract: A scanning electron microscope with a length measurement function includes an electron gun for emitting an electron beam, a measurement target region setting unit for setting a measurement region for a pattern formed on a sample, a storing unit for storing the designated measurement region, a beam blanker unit for controlling an irradiation of the electron beam depending on the measurement region, and a control unit for extracting the designated measurement region from the storing unit, interrupting the electron beam with the beam blanker unit in a region other than the measurement region, irradiating the electron beam onto the sample in the measurement region, capturing an image of the measurement region, and measuring the pattern. The measurement region may be a pair of regions having the same areas as each other.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: September 7, 2010
    Assignee: Advantest Corp.
    Inventors: Takayuki Nakamura, Toshimichi Iwai, Soichi Shida, Mitsuo Hiroyama
  • Publication number: 20080224039
    Abstract: A scanning electron microscope with a length measurement function includes an electron gun emitting an electron beam, a measurement target region setting unit for setting a measurement region for a pattern formed on a sample, a storing unit for storing the designated measurement region, a beam blanker unit for controlling an irradiation of the electron beam depending on the measurement region, and a control unit for extracting the designated measurement region from the storing unit, interrupting the electron beam with the beam blanker unit in a region other than the measurement region, irradiating the electron beam passed through the beam blanker unit onto the sample in the measurement region, capturing an image of the measurement region, and measuring the pattern. The measurement region may be represented by a pair of measurement regions, and the respective regions may have the same areas as each other.
    Type: Application
    Filed: June 21, 2007
    Publication date: September 18, 2008
    Inventors: Takayuki Nakamura, Toshimichi Iwai, Soichi Shida, Mitsuo Hiroyama
  • Patent number: 5821761
    Abstract: Test patterns are applied to an IC under test under a test pattern address by which the first fail is caused and under other test pattern addresses. A defect candidate area is moved to the position where a charged particle beam can scan the area and defect candidate wiring portions are specified. A potential data of the specified wiring is acquired for each of the test patterns and stored in a memory. This process is process performed by sequentially stepping back the stop test pattern addresses. Then, a potential data of the specified wiring in thee specified area is similarly acquired for non-defect IC. The respective potential data of the IC under test and the non-defect IC are compared to locate the mismatch test pattern address and wiring.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: October 13, 1998
    Assignee: Advantest Corporation
    Inventors: Soichi Shida, Hiroshi Kawamoto, Hironobu Niijima
  • Patent number: 5757198
    Abstract: Test patterns are applied to an IC under test under a test pattern address by which the first fail is caused and under other test pattern addresses. A defect candidate area is moved to the position where a charged particle beam can scan the area and defect candidate wiring portions are specified. A potential data of the specified wiring is acquired for each of the test patterns and stored in a memory. This process is performed by sequentially stepping back the stop test pattern addresses. Then, a potential data of the specified wiring in the specified area is similarly acquired for non-defect IC. The respective potential data of the IC under test and the non-defect IC are compared to locate the mismatch test pattern address and wiring.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: May 26, 1998
    Assignee: Advantest Corporation
    Inventors: Soichi Shida, Hiroshi Kawamoto, Hironobu Niijima
  • Patent number: 5592100
    Abstract: Test patterns are applied to an IC under test under a test pattern address by which the first fail is caused and under other test pattern addresses. A defect candidate area is moved to the position where a charged particle beam can scan the area and defect candidate wiring portions are specified. A potential data of the specified wiring is acquired for each of the test patterns and stored in a memory. This process is performed by sequentially stepping back the stop test pattern addresses. Then, a potential data of the specified wiring in the specified area is similarly acquired for non-defect IC. The respective potential data of the IC under test and the non-defect IC are compared to locate the mismatch test pattern address and wiring.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: January 7, 1997
    Assignee: Advantest Corporation
    Inventors: Soichi Shida, Hiroshi Kawamoto, Hironobu Niijima
  • Patent number: 5521517
    Abstract: The present invention allows to automatically presume a defect location of an IC using an EB tester. Under each of the conditions where a normal power supply voltage and an abnormal power supply voltage are applied to an IC respectively, test patterns are applied to the IC until the pattern address where the first defect is detected by an IC tester. At this point in time, the pattern update is stopped. Then a potential contrast image data is acquired from one of the partitioned segments of the IC surface for each of the above power supply conditions. A diffrence image data between the two potential contrast image data (normal power case and abnormal power case) is generated. This difference image data generation is repeated several times and those defference image data are summed up. A check is made to see if there is a changed portion greater than a predetermined value in each of the segments and if there is, a defect information is stored in a storage portion corresponding to the defect segment.
    Type: Grant
    Filed: July 10, 1995
    Date of Patent: May 28, 1996
    Assignee: Advantest Corporation
    Inventors: Soichi Shida, Hironobu Niijima, Hiroshi Kawamoto