Patents by Inventor Soichi Yamashita

Soichi Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230097227
    Abstract: A semiconductor device includes: a semiconductor chip having a bottom surface having a first area and a first side surface; and an electrode provided below the semiconductor chip, the electrode having a first top surface and a second side surface, and the electrode containing an electrically conductive material, wherein the first top surface has a second area larger than the first area, and at least a part of the first top surface is in contact with the bottom surface.
    Type: Application
    Filed: March 9, 2022
    Publication date: March 30, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kentaro MORI, Kazushiro NOMURA, Kenichi OHASHI, Soichi YAMASHITA, Aya MURAYOSHI
  • Publication number: 20160035624
    Abstract: According to one embodiment, a semiconductor device manufacturing method provides filling a through-hole which penetrates through a first side of substrate to a second side thereof. A seed film including copper is formed on the inner wall surface of the through-hole. A first metal layer including copper is grown bottom-up from one end of the through-hole toward the other end thereof, to partially fill the through-hole, leaving a space having a depth less than the radius of the through-hole as measured from the second side surface of the substrate. A second metal layer including nickel is conformally grown in the space from the inner peripheral surface of the through-hole to a height having a summit surface protruding from the second side surface of the substrate. A third metal layer is formed on the summit surface of the second metal layer.
    Type: Application
    Filed: October 15, 2015
    Publication date: February 4, 2016
    Inventors: Koji OGISO, Soichi YAMASHITA, Kazuhiro MURAKAMI
  • Patent number: 9190373
    Abstract: According to one embodiment, a semiconductor substrate, a redistribution trace, and a surface layer are provided, with the surface layer provided on the redistribution trace. On the semiconductor substrate, a wire and a pad electrode are formed. The redistribution trace is formed on the semiconductor substrate. The surface layer is larger in width than the redistribution trace, and extends beyond the edge of the redistribution trace.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: November 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Soichi Yamashita, Masaya Shima
  • Publication number: 20140284772
    Abstract: According to one embodiment, a semiconductor device manufacturing method provides filling a through-hole which penetrates through a first side of substrate to a second side thereof. A seed film including copper is formed on the inner wall surface of the through-hole. A first metal layer including copper is grown bottom-up from one end of the through-hole toward the other end thereof, to partially fill the through-hole, leaving a space having a depth less than the radius of the through-hole as measured from the second side surface of the substrate. A second metal layer including nickel is conformally grown in the space from the inner peripheral surface of the through-hole to a height having a summit surface protruding from the second side surface of the substrate. A third metal layer is formed on the summit surface of the second metal layer.
    Type: Application
    Filed: August 30, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji OGISO, Soichi YAMASHITA, Kazuhiro MURAKAMI
  • Patent number: 8704367
    Abstract: According to one embodiment, a semiconductor substrate, a metal film, a surface modifying layer, and a redistribution trace are provided. On the semiconductor substrate, a wire and a pad electrode are formed. The metal film is formed over the semiconductor substrate. The surface modifying layer is formed on a surface layer of the metal film and improves the adhesion with a resist pattern. The redistribution trace is formed on the metal film via the surface modifying layer.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Soichi Yamashita, Koro Nagamine, Masahiro Miyata, Tatsuo Shiotsuki, Kiyoshi Muranishi
  • Patent number: 8703600
    Abstract: An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Soichi Yamashita, Takashi Togasaki
  • Patent number: 8314491
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: November 20, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Yamashita, Tatsuo Migita, Tadashi Iijima, Masahiro Miyata, Masayuki Uchida, Takashi Togasaki, Hirokazu Ezawa
  • Publication number: 20120152168
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 21, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Patent number: 8148274
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Wada, Atsuko Sakata, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Publication number: 20120068334
    Abstract: Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 ?m or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.
    Type: Application
    Filed: September 6, 2011
    Publication date: March 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo MIGITA, Hirokazu Ezawa, Soichi Yamashita
  • Publication number: 20120056320
    Abstract: According to one embodiment, a semiconductor substrate, a metal film, a surface modifying layer, and a redistribution trace are provided. On the semiconductor substrate, a wire and a pad electrode are formed. The metal film is formed over the semiconductor substrate. The surface modifying layer is formed on a surface layer of the metal film and improves the adhesion with a resist pattern. The redistribution trace is formed on the metal film via the surface modifying layer.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 8, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo MIGITA, Hirokazu EZAWA, Soichi YAMASHITA, Koro NAGAMINE, Masahiro MIYATA, Tatsuo SHIOTSUKI, Kiyoshi MURANISHI
  • Publication number: 20120049356
    Abstract: According to one embodiment, a semiconductor substrate, a redistribution trace, and a surface layer are provided. On the semiconductor substrate, a wire and a pad electrode are formed. The redistribution trace is formed on the semiconductor substrate. The surface layer is larger in width than the redistribution trace.
    Type: Application
    Filed: August 31, 2011
    Publication date: March 1, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Soichi Yamashita, Masaya Shima
  • Publication number: 20120049367
    Abstract: According to the embodiment, a pad electrode, a protective film, an under barrier metal film, and an electrode wiring portion are provided. The pad electrode is formed on a semiconductor substrate. The protective film is formed on the semiconductor substrate so that a surface of the pad electrode is exposed. The under barrier metal film is formed on the pad electrode and the protective film. The electrode wiring portion is formed on the pad electrode via the under barrier metal film. Moreover, a surface reflectance of the under barrier metal film is 30% or more at a wavelength of 800 nm, and a diameter of the electrode wiring portion is 140 ?m or less.
    Type: Application
    Filed: August 25, 2011
    Publication date: March 1, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo MIGITA, Hirokazu Ezawa, Soichi Yamashita
  • Patent number: 8110497
    Abstract: An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection film being made of a material that is more easily oxidized than a material forming the seed film; heat-treating the protection film; exposing at least part of the seed film by removing at least part of the heat-treated protection film; forming a plating film on the seed film through electrolytic plating to be buried in the recessed portion, by supplying current to the seed film that is at least partially exposed; and removing the plating film except for a portion buried in the recessed portion.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Soichi Yamashita, Yasuyuki Sonoda, Hiroshi Toyoda, Masahiko Hasunuma
  • Patent number: 7994054
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a first metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, oxidizing at least part of the first metal film with oxidizing species remaining in the insulating film, and forming a second metal film, which includes any of a high melting point metal and a noble metal, on the first metal film, the first metal film and the second metal film sharing different metallic material.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Publication number: 20110049707
    Abstract: According to one embodiment, a semiconductor device includes an electrode pad, a protective layer, a bump, and a resin layer. The electrode pad is formed on a semiconductor substrate. The protective layer includes a pad opening formed in the position of the electrode pad. The bump is formed in the pad opening and electrically connected to the electrode pad. The resin layer has a space provided between the resin layer and the bump and is formed on the protective layer via a metal layer. The resin layer is formed by using an adhesive resin material.
    Type: Application
    Filed: August 5, 2010
    Publication date: March 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaharu Seto, Soichi Yamashita, Hirokazu Ezawa
  • Publication number: 20110024901
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer.
    Type: Application
    Filed: July 29, 2010
    Publication date: February 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Soichi Yamashita, Tatsuo Migita, Tadashi Iijima, Masahiro Miyata, Masayuki Uchida, Takashi Togasaki, Hirokazu Ezawa
  • Publication number: 20100301472
    Abstract: An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.
    Type: Application
    Filed: March 11, 2010
    Publication date: December 2, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Soichi Yamashita, Takashi Togasaki
  • Patent number: 7791202
    Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: September 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Junichi Wada, Seiichi Omoto, Masaaki Hatano, Soichi Yamashita, Kazuyuki Higashi, Naofumi Nakamura, Masaki Yamada, Kazuya Kinoshita, Tomio Katata, Masahiko Hasunuma
  • Publication number: 20100167529
    Abstract: An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection film being made of a material that is more easily oxidized than a material forming the seed film; heat-treating the protection film; exposing at least part of the seed film by removing at least part of the heat-treated protection film; forming a plating film on the seed film through electrolytic plating to be buried in the recessed portion, by supplying current to the seed film that is at least partially exposed; and removing the plating film except for a portion buried in the recessed portion.
    Type: Application
    Filed: December 23, 2009
    Publication date: July 1, 2010
    Inventors: Atsuko SAKATA, Soichi Yamashita, Yasuyuki Sonoda, Hiroshi Toyoda, Masahiko Hasunuma