Patents by Inventor Soichi Yoshida

Soichi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128360
    Abstract: Provided is a semiconductor device, comprising a semiconductor substrate and a first electrode provided above an upper surface of the semiconductor substrate. The semiconductor substrate has a first conductive type drift region. The semiconductor substrate has a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate. The semiconductor substrate has a second conductive type contact region with a higher impurity concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate. The semiconductor substrate has a trench contact that has a conductive material in an interior of a groove portion penetrating the contact region, the conductive material being in contact with at least a part of the semiconductor substrate, and connected to the first electrode.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Inventor: Soichi YOSHIDA
  • Patent number: 11958355
    Abstract: An accelerator pedal system includes a pedal lever, a lock mechanism, an actuator, and an ECU. The pedal lever operates according to a step-on operation. The lock mechanism can restrict an operation of the pedal lever. The actuator switches between a locked state in which the operation of the pedal lever is restricted by the lock mechanism and an unlocked state in which the operation of the pedal lever is not restricted. The ECU includes a lock operation determination unit and an actuator control unit. The lock operation determination unit unlocks the pedal lever when an approaching object from behind is detected during a travel of a vehicle in the locked state.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: April 16, 2024
    Assignee: DENSO CORPORATION
    Inventors: Soichi Kinouchi, Yuusuke Yoshida, Takuto Kita, Hideyuki Mori, Shinji Komatsu
  • Patent number: 11955540
    Abstract: Provided is a semiconductor device, comprising a semiconductor substrate; and an emitter electrode provided above an upper surface of the semiconductor substrate; wherein the semiconductor substrate has: a first conductive type drift region; a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate; a second conductive type contact region with a higher doping concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate; a trench contact of a conductive material provided to connect to the emitter electrode and penetrate the contact region; and a second conductive type high-concentration plug region with a higher doping concentration than the contact region, which is provided in contact with a bottom portion of the trench contact.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Soichi Yoshida
  • Patent number: 11938815
    Abstract: An accelerator pedal system includes a pedal lever configured to perform an operation in accordance with a step-on operation, a lock mechanism configured to restrict the operation of the pedal lever, and an actuator configured to switch between a locked state in which the operation of the pedal lever is restricted by the lock mechanism and an unlocked state in which the operation of the pedal lever is free from restriction by the lock mechanism. In the accelerator pedal system, a controller configured to change an energization amount to the actuator when a disturbance is detected during a vehicle traveling in the locked state. Thus, the lock state can be suitably controlled.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: March 26, 2024
    Assignee: DENSO CORPORATION
    Inventors: Soichi Kinouchi, Yuusuke Yoshida, Takuto Kita, Hideyuki Mori, Shinji Komatsu
  • Publication number: 20240079286
    Abstract: In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Inventors: Motoyoshi KUBOUCHI, Soichi YOSHIDA
  • Patent number: 11912126
    Abstract: An accelerator pedal system includes a pedal lever, a lock mechanism, an actuator, and an ECU. The lock mechanism can restrict the operation of the pedal lever. The actuator switches between a locked state in which the operation of the pedal lever is restricted by the lock mechanism and an unlocked state in which the operation of the pedal lever is not restricted. The ECU includes a lock operation determination unit and an actuator control unit. The lock operation determination unit resumes the locked state by the drive of the actuator after a release from the locked state due to the step-on operation of the pedal lever during the automatic drive control in the locked state, when (i) the automatic drive control is continued or (ii) a resuming of the automatic drive control is detected.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: February 27, 2024
    Assignee: DENSO CORPORATION
    Inventors: Yuusuke Yoshida, Soichi Kinouchi, Takuto Kita, Hideyuki Mori
  • Publication number: 20240030324
    Abstract: Provided is a semiconductor device including: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region arranged sandwiching the active portion in a top view, provided on the semiconductor substrate; an emitter electrode arranged above the active portion; and a pad arranged above the first well region, away from the emitter electrode, wherein the emitter electrode is provided above the second well region. The provided semiconductor device further includes a peripheral well region arranged enclosing the active portion in a top view, wherein the first well region and the second well region may protrude to the center side of the active portion rather than the peripheral well region.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 25, 2024
    Inventors: Atsushi SHOJI, Soichi YOSHIDA
  • Publication number: 20240021607
    Abstract: Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Inventors: Tomoyuki OBATA, Soichi YOSHIDA, Tetsutaro IMAGAWA, Seiji MOMOTA
  • Patent number: 11869960
    Abstract: Provided is a semiconductor device, comprising a semiconductor substrate; and an emitter electrode provided above an upper surface of the semiconductor substrate; wherein the semiconductor substrate has: a first conductive type drift region; a second conductive type base region provided between the drift region and the upper surface of the semiconductor substrate; a second conductive type contact region with a higher doping concentration than the base region, which is provided between the base region and the upper surface of the semiconductor substrate; a trench contact of a conductive material provided to connect to the emitter electrode and penetrate the contact region; and a second conductive type high-concentration plug region with a higher doping concentration than the contact region, which is provided in contact with a bottom portion of the trench contact.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: January 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Soichi Yoshida
  • Patent number: 11830782
    Abstract: In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: November 28, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motoyoshi Kubouchi, Soichi Yoshida
  • Publication number: 20230369137
    Abstract: A semiconductor device includes trench portions arrayed in a first direction on an upper surface side of a semiconductor substrate, a first conductivity type lower surface region provided in a part of a lower surface of the semiconductor substrate, a second conductivity type base region provided on the upper surface side, a first conductivity type first region disposed between the base region and the lower surface region, a first conductivity type upper surface region provided on an upper surface of the semiconductor substrate, and a second conductivity type bottom region disposed continuously in the first direction to be in contact with bottom portions of the trench portions. In a cross section along the first direction and perpendicular to the upper and lower surfaces and passing through the lower surface region, one end portion of the bottom region in the first direction locates directly above the lower surface region.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 16, 2023
    Inventors: Motoyoshi KUBOUCHI, Kosuke YOSHIDA, Soichi YOSHIDA, Koh YOSHIKAWA, Nao SUGANUMA
  • Patent number: 11810914
    Abstract: Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: November 7, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tomoyuki Obata, Soichi Yoshida, Tetsutaro Imagawa, Seiji Momota
  • Publication number: 20230335599
    Abstract: A device includes a substrate with upper/lower surfaces, including hydrogen containing region having hydrogen chemical concentration peaks in a depth direction. A carrier concentration distribution of the hydrogen containing region includes a first carrier concentration peak, a second carrier concentration peak closest to the first carrier concentration peak, a third carrier concentration peak arranged closer to the upper surface than the second carrier concentration peak, a first inter peak region arranged between the first and second carrier concentration peaks, a second inter peak region arranged between the second and third carrier concentration peaks, and an inter-peaks concentration peak arranged in the second inter peak region such that the concentration peak does not overlap the hydrogen chemical concentration peaks in the second and third carrier concentration peaks. A local minimum value of a carrier concentration in the first inter peak region is smaller than that of the second inter peak region.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 19, 2023
    Inventors: Yoshiharu KATO, Toru AJIKI, Tohru SHIRAKAWA, Misaki TAKAHASHI, Kaname MITSUZUKA, Takashi YOSHIMURA, Yuichi ONOZAWA, Hiroshi TAKISHITA, Soichi YOSHIDA
  • Patent number: 11777020
    Abstract: Provided is a semiconductor device including: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region arranged sandwiching the active portion in a top view, provided on the semiconductor substrate; an emitter electrode arranged above the active portion; and a pad arranged above the first well region, away from the emitter electrode, wherein the emitter electrode is provided above the second well region. The provided semiconductor device further includes a peripheral well region arranged enclosing the active portion in a top view, wherein the first well region and the second well region may protrude to the center side of the active portion rather than the peripheral well region.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: October 3, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Atsushi Shoji, Soichi Yoshida
  • Publication number: 20230299078
    Abstract: There is provided a semiconductor device that includes a transistor portion and a diode portion, the semiconductor device including a drift region, a base region, an emitter region, and a plurality of trench portions, in which the transistor portion has a boundary region provided to be adjacent to the diode portion, a lifetime control region is provided from the diode portion, across the boundary region, to the transistor portion provided with the emitter region, in an array direction of the plurality of trench portions, the boundary region has a plug region of a second conductivity type which is provided to extend in an extension direction of the plurality of trench portions and which has a doping concentration higher than that of the base region, and a contact region and the base region are alternately arranged in the extension direction, at a front surface in the boundary region.
    Type: Application
    Filed: May 21, 2023
    Publication date: September 21, 2023
    Inventor: Soichi YOSHIDA
  • Patent number: 11742249
    Abstract: A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.
    Type: Grant
    Filed: September 5, 2022
    Date of Patent: August 29, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motoyoshi Kubouchi, Kosuke Yoshida, Soichi Yoshida, Koh Yoshikawa, Nao Suganuma
  • Patent number: 11715771
    Abstract: Provided is a semiconductor device comprising a semiconductor substrate, wherein the semiconductor substrate includes a hydrogen containing region including hydrogen, and the hydrogen containing region includes a high concentration region with a higher carrier concentration than a virtual carrier concentration determined based on a concentration of hydrogen included and an activation ratio of hydrogen. The semiconductor substrate includes an N type drift region, an N type emitter region that has a higher carrier concentration than that in the drift region, a P type base region, a P type collector region provided to be in contact with a lower surface of the semiconductor substrate, and an N type buffer region that is provided between the collector region and the drift region, and has a higher carrier concentration than that in the drift region, and the hydrogen containing region is included in the buffer region.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 1, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiharu Kato, Toru Ajiki, Tohru Shirakawa, Misaki Takahashi, Kaname Mitsuzuka, Takashi Yoshimura, Yuichi Onozawa, Hiroshi Takishita, Soichi Yoshida
  • Publication number: 20230040096
    Abstract: A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.
    Type: Application
    Filed: September 5, 2022
    Publication date: February 9, 2023
    Inventors: Motoyoshi KUBOUCHI, Kosuke YOSHIDA, Soichi YOSHIDA, Koh YOSHIKAWA, Nao SUGANUMA
  • Patent number: 11552165
    Abstract: A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 10, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Soichi Yoshida
  • Publication number: 20220328668
    Abstract: Provided is a semiconductor device including: a first trench portion having a predetermined first trench length; a second trench portion having a second trench length longer than the first trench length; a first gate runner portion configured to be electrically connected to an end portion of the first trench portion; and a second gate runner portion configured to be electrically connected to the first gate runner portion and electrically connected to an end portion of the second trench portion. A resistivity per unit length of the first gate runner portion is larger than a resistivity per unit length of the second gate runner portion.
    Type: Application
    Filed: February 24, 2022
    Publication date: October 13, 2022
    Inventors: Shigeki SATO, Soichi YOSHIDA, Kouji ASAHI, Seiji MOMOTA