Abstract: A parallax image generation device generates motion vectors of a first image with respect to a second image, the first image including a blank region that does not contain any image information and an effective region that contains image information. The parallax image generation device includes a motion vector search circuit configured to generate motion vectors of blocks of the effective region and blocks of the blank region, at least one of the blocks of the blank region being generated from a motion vector of a block of the effective region, and an output control circuit connected to the motion vector search circuit and configured to output the motion vectors of the blocks of the effective region and the blank region that have been generated by the motion vector search circuit in a raster scan order.

Abstract: A processor for determining whether or not a first position of an image sensor corresponding to a pixel of an image sensor is included in areas of the image sensor corresponding to microlenses of the image sensor includes a cache configured to store one or more second positions of the image sensor corresponding to centers of the microlenses, each of the second positions being included in one or more of multiple regions defining an entire region of the image sensor, and a first controller configured to cause one or more of the second positions to be stored in the cache. Whether or not the first position is included in the areas corresponding to the microlenses is determined based on the second positions stored in the cache.

Abstract: According to one embodiment, a cache unit transferring data from a memory connected to the cache unit via a bus incompatible with a critical word first (CWF) to an L1-cache having a first line size and connected to the cache unit via a bus compatible with the CWF. The unit includes cache and un-cache controllers. The cache controller includes an L2-cache and a request converter. The L2-cache has a second line size greater than or equal to the first line size. The request converter converts a first refill request into a second refill request when a head address of a burst transfer of the first refill request is in the L2-cache. The un-cache controller transfers the second refill request to the memory, receives data to be processed corresponding to the second refill request from the memory, and transfers the received data to the L1-cache.

Abstract: According to one embodiment, a cache unit transferring data from a memory connected to the cache unit via a bus incompatible with a critical word first (CWF) to an L1-cache having a first line size and connected to the cache unit via a bus compatible with the CWF. The unit includes cache and un-cache controllers. The cache controller includes an L2-cache and a request converter. The L2-cache has a second line size greater than or equal to the first line size. The request converter converts a first refill request into a second refill request when a head address of a burst transfer of the first refill request is in the L2-cache. The un-cache controller transfers the second refill request to the memory, receives data to be processed corresponding to the second refill request from the memory, and transfers the received data to the L1-cache.

Abstract: An instruction cache system includes an instruction-cache data storage unit that stores cache data per index, and an instruction cache controller that compresses and writes the cache data in the instruction-cache data storage unit, and controls a compression ratio of the written cache data. The instruction cache controller calculates a memory capacity of a redundant area generated due to compression in a memory area belonging to an index, in which n pieces of cache data are written based on the controlled compression ratio, to compress and write new cache data in the redundant area based on the calculated memory capacity.

Abstract: A multiprocessor according to an embodiment of the present invention comprises: a provisional determination unit that provisionally determines one transfer source for each transfer destination by performing predetermined prediction processing based on monitoring of transfer of cache data among cache memories. A data transfer unit activates, after a provisional determination result of the provisional determination unit is obtained, only a tag cache corresponding to the provisionally-determined one transfer source when the transfer of the cache data is performed and determines whether cache data corresponding to a refill request is cached referring to only the activated tag cache.

Abstract: A processor system includes a plurality of pipeline stages, a controller, and a transfer path. The plurality of pipeline stages is subjected to processing. The controller determines whether or not each of the executable instructions to be processed in the pipeline stages requires processing in a succeeding pipeline stage. The transfer path, if the controller determines the executable instruction does not require the processing in the succeeding pipeline stage, skips the pipeline stage including the unnecessary processing.

Abstract: An instruction cache system includes an instruction-cache data storage unit that stores cache data per index, and an instruction cache controller that compresses and writes the cache data in the instruction-cache data storage unit, and controls a compression ratio of the written cache data. The instruction cache controller calculates a memory capacity of a redundant area generated due to compression in a memory area belonging to an index, in which n pieces of cache data are written based on the controlled compression ratio, to compress and write new cache data in the redundant area based on the calculated memory capacity.

Abstract: An arithmetic processing apparatus includes a cache block which stores a plurality of instruction codes from a main memory, a central processing unit which fetch-accesses the cache block and sequentially loads and executes the plurality of instruction codes, and a repeat buffer which stores an instruction code group corresponding to a buffer size, the instruction code group ranging from a head instruction code to a terminal instruction code among the head instruction code to an end instruction code of a repeat block repeatedly executed in the processing program, in the plurality of instruction codes stored in the cache block. The arithmetic processing apparatus further includes an instruction cache control unit which performs control so that the instruction code group stored in the repeat buffer is selected and supplied to the central processing unit when the repeat block is repeatedly executed.

Abstract: A processor system according to an aspect of the present invention has a pipeline. The pipeline includes a cache memory, an instruction fetch buffer which stores commands, an execution module which requests data access to the cache memory, a tag memory which outputs information related to the data access of the execution module, and an arbitration circuit which arbitrates access to the cache memory based on entry information of the instruction fetch buffer and the information related to the data access from the tag memory.