Abstract: A data processing machine including a CPU which is configured to operate with an adjustable (variable) clock frequency. The clock frequency is adjusted in accordance with a clock change request signal. A plurality of clock change request signals have respective priority orders. A plurality of clock frequencies are prepared for the clock change request signals. When two or more clock change request signals are input, one of them is selected based on the priority order. The clock signal (clock frequency) to be applied to the CPU is changed in accordance with the selected clock change request signal. The data processing machine can adjust a timing for memory access to an optimal timing when the clock frequency is adjusted. The data processing machine can also deal with various clock frequency change requests.

Abstract: A power supply control circuit includes a comparator which compares the supply voltage (VDDV) with a predetermined reference voltage (VREF) and supplies a comparison signal (CMP) when the supply voltage (VDDV) reaches the reference voltage (VREF); and a controller which initiates wake-up operation of the circuit block in accordance with the comparison signal (CMP) of the comparator.

Abstract: A data processing machine including a CPU which is configured to operate with an adjustable (variable) clock frequency. The clock frequency is adjusted in accordance with a clock change request signal. A plurality of clock change request signals have respective priority orders. A plurality of clock frequencies are prepared for the clock change request signals. When two or more clock change request signals are input, one of them is selected based on the priority order. The clock signal (clock frequency) to be applied to the CPU is changed in accordance with the selected clock change request signal. The data processing machine can adjust a timing for memory access to an optimal timing when the clock frequency is adjusted. The data processing machine can also deal with various clock frequency change requests.

Abstract: An operating condition of an operating circuit is provided to a register, a counter is set in accordance with an operating condition signal stored in the register, and the counter outputs a reset signal to the operating circuit. The operating condition signal indicates a reset delay period which is equal to the sum of a shortest rise time of power supply voltage and a reset period to reset the counter after the power supply voltage has settled.

Abstract: An operating condition of an operating circuit is provided it to a register, a counter is set in accordance with an operating condition signal stored in the register, and the counter outputs a reset signal to the operating circuit. The operating condition signal indicates a reset delay period which is equal to the sum of a shortest rise time of power supply voltage and a reset period to reset the counter after the power supply voltage has settled.

Abstract: A power supply control circuit includes a comparator which compares the supply voltage (VDDV) with a predetermined reference voltage (VREF) and supplies a comparison signal (CMP) when the supply voltage (VDDV) reaches the reference voltage (VREF); and a controller which initiates wake-up operation of the circuit block in accordance with the comparison signal (CMP) of the comparator.