Patents by Inventor Soichiro KITAZAKI
Soichiro KITAZAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10121797Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.Type: GrantFiled: September 19, 2016Date of Patent: November 6, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shigeki Kobayashi, Satoshi Konagai, Atsushi Konno, Kenta Yamada, Masaaki Higuchi, Masao Shingu, Soichiro Kitazaki, Yoshimasa Mikajiri
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Publication number: 20170243873Abstract: According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a semiconductor layer facing the control gate electrodes; and a gate insulating layer provided between the control gate electrode and the semiconductor layer. The stacked body comprises: a first metal layer configuring the control gate electrode; a first barrier metal layer contacting an upper surface of this first metal layer; a first silicon nitride layer contacting an upper surface of this first barrier metal layer; a first inter-layer insulating layer contacting an upper surface of this first silicon nitride layer; a second barrier metal layer contacting a lower surface of the first metal layer; a second silicon nitride layer contacting a lower surface of this second barrier metal layer; and a second inter-layer insulating layer contacting a lower surface of this second silicon nitride layer.Type: ApplicationFiled: September 19, 2016Publication date: August 24, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shigeki KOBAYASHI, Satoshi KONAGAI, Atsushi KONNO, Kenta YAMADA, Masaaki HIGUCHI, Masao SHINGU, Soichiro KITAZAKI, Yoshimasa MIKAJIRI
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Patent number: 9111964Abstract: According one embodiment, a nonvolatile semiconductor memory device, includes: a stacked body, and each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the a stacked body; a first interlayer insulating film on the stacked body; a gate electrode on the first interlayer insulating film; a second interlayer insulating film on the gate electrode; a semiconductor layer extended from an upper end of the second interlayer insulating film to a lower end of the stacked body; a first insulating film between the semiconductor layer and each of the plurality of electrode layers; and a second insulating film between the semiconductor layer and the gate electrode, a thickness of the semiconductor layer provided above an upper end of the gate electrode being thicker than a thickness of the semiconductor layer provided below the upper end of the gate electrode.Type: GrantFiled: September 6, 2013Date of Patent: August 18, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Sato, Soichiro Kitazaki, Ryu Kato, Masaru Kito, Ryota Katsumata
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Patent number: 9076820Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of insulating isolation sections provided so as to extend in a first direction, isolate the stacked body in a second direction, and have a projection projecting from the stacked body. Each insulating isolation section has a side wall including recessed sections and projected sections repeated along the first direction. The method includes forming a sidewall film on a side wall of the projection of the insulating isolation section, and forming a plurality of first holes surrounded by the sidewall film and isolated by the sidewall film in the first direction, between the plurality of insulating isolation sections. The method includes forming a second hole in the stacked body provided under the first hole by etching with the insulating isolation section and the sidewall film used as a mask.Type: GrantFiled: August 31, 2012Date of Patent: July 7, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Soichiro Kitazaki, Masaru Kidoh, Mitsuru Sato, Ryota Katsumata, Tadashi Iguchi
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Publication number: 20140284693Abstract: According one embodiment, a nonvolatile semiconductor memory device, includes: a stacked body, and each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the a stacked body; a first interlayer insulating film on the stacked body; a gate electrode on the first interlayer insulating film; a second interlayer insulating film on the gate electrode; a semiconductor layer extended from an upper end of the second interlayer insulating film to a lower end of the stacked body; a first insulating film between the semiconductor layer and each of the plurality of electrode layers; and a second insulating film between the semiconductor layer and the gate electrode, a thickness of the semiconductor layer provided above an upper end of the gate electrode being thicker than a thickness of the semiconductor layer provided below the upper end of the gate electrode.Type: ApplicationFiled: September 6, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Mitsuru SATO, Soichiro KITAZAKI, Ryu KATO, Masaru KITO, Ryota KATSUMATA
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Publication number: 20130228852Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of insulating isolation sections provided so as to extend in a first direction, isolate the stacked body in a second direction, and have a projection projecting from the stacked body. Each insulating isolation section has a side wall including recessed sections and projected sections repeated along the first direction. The method includes forming a sidewall film on a side wall of the projection of the insulating isolation section, and forming a plurality of first holes surrounded by the sidewall film and isolated by the sidewall film in the first direction, between the plurality of insulating isolation sections. The method includes forming a second hole in the stacked body provided under the first hole by etching with the insulating isolation section and the sidewall film used as a mask.Type: ApplicationFiled: August 31, 2012Publication date: September 5, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Soichiro KITAZAKI, Masaru KIDOH, Mitsuru SATO, Ryota KATSUMATA, Tadashi IGUCHI