Patents by Inventor Soichiro Ozawa

Soichiro Ozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Ferroelectric semiconductor memory device and a fabrication process thereof
    Patent number: 6777287
    Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17 &mgr;m2 or less.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: August 17, 2004
    Assignee: Fujitsu Limited
    Inventors: Soichiro Ozawa, Shan Sun, Hideyuki Noshiro, George Hickert, Katsuyoshi Matsuura, Fan Chu, Takeyasu Saito
  • Process for producing a strontium ruthenium oxide protective layer on a top electrode
    Patent number: 6674633
    Abstract: A method for the fabrication of a cap layer on a top electrode layer of a ferroelectric capacitor includes the steps of depositing an amorphous layer, usually made of Sr(x)Ru(y)O3, on the top electrode and then annealing the amorphous layer in two stages in order convert the amorphous layer into the cap layer. The first anneal is performed at 500° C. to 700° C. in a non-oxidizing atmosphere, such as nitrogen, and converts the amorphous layer into a crystallized layer of Sr(x)Ru(y)O3. The second anneal is performed at 300° C. to 500° C. in an oxidizing atmosphere, such as oxygen, and converts the crystallized layer into the cap layer. The method is applied to the formation of a ferroelectric capacitor element of an integrated semiconductor device.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: January 6, 2004
    Assignee: Fujitsu Limited
    Inventors: Shan Sun, George Hickert, Katsuyoshi Matsuura, Takeyasu Saito, Soichiro Ozawa, Naoyuki Satoh, Mitsushi Fujiki, Satoru Mihara, Jeffrey S. Cross, Yoshimasa Horii
  • Ferroelectric semiconductor memory device and a fabrication process thereof
    Publication number: 20030205743
    Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17 &mgr;m2 or less.
    Type: Application
    Filed: May 23, 2003
    Publication date: November 6, 2003
    Inventors: Soichiro Ozawa, Shan Sun, Hideyuki Noshiro, George Hickert, Katsuyoshi Matsuura, Fan Chu, Takeyasu Saito
  • Ferroelectric semiconductor memory device and a fabrication process thereof
    Patent number: 6617626
    Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17/&mgr;m2 or less.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: September 9, 2003
    Assignee: Fujitsu Limited
    Inventors: Soichiro Ozawa, Shan Sun, Hideyuki Noshiro, George Hickert, Katsuyoshi Matsuura, Fan Chu, Takeyasu Saito
  • Ferroelectric semiconductor memory device and a fabrication process thereof
    Publication number: 20020158278
    Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17/&mgr;m2 or less.
    Type: Application
    Filed: February 28, 2001
    Publication date: October 31, 2002
    Inventors: Soichiro Ozawa, Shan Sun, Hideyuki Noshiro, George Hickert, Katsuyoshi Matsuura, Fan Chu, Takeyasu Saito
  • Process for producing a strontium ruthenium oxide protective layer on a top electrode
    Publication number: 20020149040
    Abstract: A method for the fabrication of a cap layer on a top electrode layer of a ferroelectric capacitor includes the steps of depositing an amorphous layer, usually made of Sr(x)Ru(y)O3, on the top electrode and then annealing the amorphous layer in two stages in order convert the amorphous layer into the cap layer. The first anneal is performed at 500° C. to 700° C. in a non-oxidizing atmosphere, such as nitrogen, and converts the amorphous layer into a crystallized layer of Sr(x)Ru(y)O3. The second anneal is performed at 300° C. to 500° C. in an oxidizing atmosphere, such as oxygen, and converts the crystallized layer into the cap layer. The method is applied to the formation of a ferroelectric capacitor element of an integrated semiconductor device.
    Type: Application
    Filed: February 28, 2001
    Publication date: October 17, 2002
    Inventors: Shan Sun, George Hickert, Katsuyoshi Matsuura, Takeyasu Saito, Soichiro Ozawa, Naoyuki Satoh, Mitsushi Fujiki, Satoru Mihara, Jeffrey S. Cross, Yoshimasa Horii
  • Semiconductor device manufacturing method including ashing process
    Patent number: 6044850
    Abstract: Ashing process of a resist pattern used in a semiconductor device manufacturing method is conducted by exposing the resist, the wirings, and their peripheral regions to a first atmosphere which includes a first product obtained by plasmanizing a gas containing water at a rate of more than 30 flow rate %, and placing the resist in a second atmosphere which includes a second product obtained by plasmanizing an oxygen mixed gas which contains an oxygen gas as a principal component before or after or before and after the exposing step.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: April 4, 2000
    Assignee: Fujitsu Limited
    Inventors: Soichiro Ozawa, Satoru Mihara, Kunihiko Nagase, Masaaki Aoyama, Naoki Nishida