Abstract: A gate driving apparatus includes a first stage which outputs a first gate output signal, and a second stage which outputs a second gate output signal. The first stage includes: a transistor which includes a gate electrode, a source electrode and a drain electrode; and a dummy transistor which includes a dummy gate electrode, a dummy source electrode and a dummy drain electrode. The gate electrode receives the second gate output signal, and the dummy source electrode is connected to the source electrode or the drain electrode of the transistor and prevents static electricity from flowing to the first stage.

Abstract: A gate driving apparatus includes a first stage which outputs a first gate output signal, and a second stage which outputs a second gate output signal. The first stage includes: a transistor which includes a gate electrode, a source electrode and a drain electrode; and a dummy transistor which includes a dummy gate electrode, a dummy source electrode and a dummy drain electrode. The gate electrode receives the second gate output signal, and the dummy source electrode is connected to the source electrode or the drain electrode of the transistor and prevents static electricity from flowing to the first stage.

Abstract: A gate driving apparatus includes a first stage which outputs a first gate output signal, and a second stage which outputs a second gate output signal. The first stage includes: a transistor which includes a gate electrode, a source electrode and a drain electrode; and a dummy transistor which includes a dummy gate electrode, a dummy source electrode and a dummy drain electrode. The gate electrode receives the second gate output signal, and the dummy source electrode is connected to the source electrode or the drain electrode of the transistor and prevents static electricity from flowing to the first stage.

Abstract: A gate driving apparatus includes a first stage which outputs a first gate output signal, and a second stage which outputs a second gate output signal. The first stage includes: a transistor which includes a gate electrode, a source electrode and a drain electrode; and a dummy transistor which includes a dummy gate electrode, a dummy source electrode and a dummy drain electrode. The gate electrode receives the second gate output signal, and the dummy source electrode is connected to the source electrode or the drain electrode of the transistor and prevents static electricity from flowing to the first stage.

Abstract: A flash memory device is provided with reduced size and method of accessing the same. In the flash memory device, since memory cells are each coupled to a plurality of bitline pairs and is configured to be accessed by a single page buffer circuit and a single Y-gate circuit, it is possible to reduce the number of the Y-gate circuits and thereby to shrink down the size of the flash memory device.

Abstract: An intrusion detection system and method of a wireless network providing wireless communication to one or more wireless terminal, and an intrusion detection sensor capable of detecting attacks against wireless network are provided. The intrusion detection system of a wireless network includes: an access point providing wireless communication to a wireless terminal; and an intrusion detection sensor examining packets transmitted and received between the access point and a wireless terminal according to a predetermined detection rule. The access point transmits confirmation information on whether or not an event packet, including critical information on whether or not a wireless line connection between the access point and the wireless terminal is established, is transmitted, to the intrusion detection sensor, and the intrusion detection sensor examines an event packet by using the confirmation information.

Abstract: A page buffer of a non-volatile memory device and a method for programming and reading the same is provided. The page buffer includes a first latch unit and one or more second latch units for storing data, transfer units connected between the first latch unit and the second latch units for transferring the data stored in the first latch unit to the second latch units, a path select unit that that senses data from bit lines and stores the sensed data in the first latch unit, and, in a program operation, transfers the data from the first and second latch units to the bit lines, a sensing unit for allowing the path select unit to sense data or the data received from the bit lines to be stored in the first latch unit, and a data I/O unit.

Abstract: A heat exchanger is provided that is capable of performing heat exchange more efficiently by using slits. The heat exchanger includes a refrigerant pipe for allowing a refrigerant to flow therethrough, at least one fin disposed such that the refrigerant pipe penetrates through the at least one fin for performing heat exchange with air passing by the at least one fin, at least one slit formed by partially cutting out the at least one fin, and at least one slit fin extending from the at least one fin adjacent to one side edge of the at least one slit for inducing turbulent flow in air flowing along a flow channel spaced a predetermined distance from the at least one fin. The width of the at least one slit is greater than or equal to ? of the diameter of the refrigerant pipe. Turbulent flow is induced in air flowing through the heat exchanger by one side edge of the slit disposed downstream of the flow direction of air. Consequently, heat exchange efficiency of the heat exchanger is improved.

Abstract: Provided is related to a flash memory device, comprising an input receiver to input data, a data selector for generating a plurality of control signals in accordance with recognizing whether the input data in the data receiver is either the data to be programmed or the data to be erased, a data load path being enabled for data to be programmed while disabled for data to be erased, in response to the control signal, and a page buffer for storing the input data from the data load path. The present invention improves a data loading speed and enhances power consumption property by reducing current dissipation.

Abstract: A server certificate verification method in a terminal during. Extensible Authentication Protocol authentication for Internet access is provided, the method including (a) receiving a server certificate from a wireless LAN authentication server, and transmitting a server certificate verification request message of the server certificate to a wireless LAN authentication server via a wireless LAN access server; (b) transmitting by the wireless LAN authentication server an On-line Certificate Status Protocol request message to an On-line Certificate Status Protocol server to verify the server certificate; (c) receiving a result of the server certificate verification performed by the OCSP server using an Extensible Authentication Protocol packet from the wireless LAN authentication server; and (d) determining whether the result of the server certificate verification is valid.