Abstract: A circuit arrangement for multiplying the frequency f.sub.x of an input signal by digital techniques is disclosed. A digital counter driven by a reference oscillator establishes the ratio of the reference frequency to signal frequency. The binary representation of this ratio is applied to a binary divider circuit and divided by the frequency multiplying factor M. The quotient produced is applied to program a presettable binary down-counter operating on the reference frequency f.sub.o to produce an output frequency Mf.sub.x where the components of the reference frequency are caused to cancel out.